Declared mm_file component in mm_file_pkg.vhd to avoid having to do it in each tb or mmm file.

boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd

@@ -108,23 +108,6 @@ ARCHITECTURE str OF mmm_unb2_minimal IS
 
   SIGNAL i_reset_n         : STD_LOGIC;
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;
-
 BEGIN
 
   ----------------------------------------------------------------------------

boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd

@@ -281,23 +281,6 @@ ARCHITECTURE str OF mmm_unb2_test IS
   SIGNAL sim_eth1g_eth1_reg_mosi                   : t_mem_mosi;
   SIGNAL i_reset_n                                 : STD_LOGIC;
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;
-
 BEGIN
 
   ----------------------------------------------------------------------------