Update tc --sim.

boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd

@@ -40,7 +40,7 @@
 -- > tc_unb2_test_eth_sim_stop.sh
 -- or use python script:
 -- . use -n 10000 packets/s to have 1 packet per BG sync interval of 100 us in sim
--- > tc_unb2_test_eth.py --gn2 0 --stream 0 -n 10000 --dest loopback --range 1000,1001,1 --interval 100 --scheme tx --sim
+-- > tc_unb2_test_eth.py --gn2 0 --stream 0 --dest loopback -r 10000 --sizes 1000 --interval 100 --scheme tx_rx --sim
 -- stop simulation.
 LIBRARY IEEE;
 USE IEEE.std_logic_1164.ALL;

boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd

@@ -25,6 +25,7 @@
 -- Purpose: Tb to try loading design in simulator
 -- Description:
 -- Usage:
+-- > as 12
 -- > run 1 us.
 --
 -- Or try some MM:
@@ -32,6 +33,11 @@
 -- On command line do:
 -- > python $UPE_GEAR/peripherals/util_system_info.py --gn 0 -n 0 -v 5 --sim
 --
+-- To run BG eth_tester in simuation do:
+-- > run -a (or run 1 ms)
+-- . use -n 10000 packets/s to have 1 packet per BG sync interval of 100 us in sim
+-- > tc_unb2_test_eth.py --gn2 0 --stream 4 --dest loopback -r 10000 --sizes 1000 --interval 100 --scheme tx_rx --sim
+-- stop simulation.
 
 LIBRARY IEEE;
 USE IEEE.std_logic_1164.ALL;
@@ -57,6 +63,8 @@ BEGIN
   eth_clk(0) <= NOT eth_clk(0) AFTER 8 ns;
   eth_clk(1) <= NOT eth_clk(1) AFTER 8 ns;
 
+  pps <= NOT pps AFTER 80 ns;
+
   eth_sgin <= eth_sgout;  -- loopback eth0 and eth1
 
   u_unb2c_test_1GbE_II : ENTITY work.unb2c_test_1GbE_II