Added out_siso.ready sample flow control. Added purpose and description.

libraries/base/diag/src/vhdl/diag_block_gen.vhd

@@ -19,6 +19,46 @@
 --
 -------------------------------------------------------------------------------
 
+-- Purpose: Block generator repeating a data pattern
+-- Description:
+--   The data pattern is read via the buf_* MM interface. The output data
+--   block is controlled via ctrl of type t_diag_block_gen with fields:
+--
+--     enable             : sl  -- block enable immediately
+--     enable_sync        : sl  -- block enable at next en_sync pulse
+--     samples_per_packet : slv -- number of valid per block, from sop to eop
+--     blocks_per_sync    : slv -- number of blocks per sync interval
+--     gapsize            : slv -- number of clk cycles between blocks, so
+--                                 between last eop and next sop
+--     mem_low_adrs       : slv -- block start address at MM interface
+--     mem_high_adrs      : slv -- end address at MM interface
+--     bsn_init           : slv -- BSN of first output block
+--                                          
+--   The MM reading starts at mem_low_adrs when the BG is first enabled. If
+--   the mem_high_adrs-mem_low_adrs+1 < samples_per_packet then the reading
+--   wraps and continues from mem_low_adrs. For every new block the reading
+--   continues where it left in the previous block. This MM reading scheme
+--   allows using a periodic data pattern that can extends accross blocks and
+--   sync intervals, because is continues for as long as the BG remains
+--   enabled.
+--
+--   The input en_sync can be used as trigger to start multiple BG at the same
+--   clk cycle. The BG creates a out_sosi.sync at the first sop and the sop of
+--   every blocks_per_sync.
+--
+--   The current block is finished properly after enable gows low, to ensure 
+--   that all blocks have the same length. A new ctrl is accepted after a
+--   current block has finished, to ensure that no fractional blocks will 
+--   enter the stream.
+--
+--   The BG supports block flow control via out_siso.xon. The BG also supports
+--   sample flow control via out_siso.ready.
+--
+--   The read data is resized and output as unsigned via:
+--   . out_sosi.data(g_buf_dat_w-1:0).
+--   The read data is also output as complex data via:
+--   . out_sosi.im(g_buf_dat_w  -1:g_buf_dat_w/2)
+--   . out_sosi.re(g_buf_dat_w/2-1:            0)
 
 library IEEE, common_lib, dp_lib;
 use IEEE.STD_LOGIC_1164.ALL;
@@ -132,47 +172,51 @@ begin
           end if;
           
         when s_block =>
-          v.rd_ena := '1';
-          if r.samples_cnt = 0 and r.blocks_cnt = 0 then 
-            v.pls_sync    := '1';                      -- Always start with a pulse sync          
-            v.blk_sync    := '1';
-            v.sop         := '1';
-            v.samples_cnt := v.samples_cnt + 1; 
-          elsif r.samples_cnt = 0 then
-            v.sop         := '1';
-            v.samples_cnt := v.samples_cnt + 1; 
-          elsif r.samples_cnt >= v_samples_per_packet-1 and v_gapsize = 0 and r.blocks_cnt >= v_blocks_per_sync-1 then 
-            v.eop         := '1'; 
-            v.ctrl_reg    := ctrl;      -- accept new control settings at end of block when gapsize=0
-            v.samples_cnt := 0; 
-            v.blocks_cnt  := 0;
-          elsif r.samples_cnt >= v_samples_per_packet-1 and v_gapsize = 0 then 
-            v.eop         := '1'; 
-            v.ctrl_reg    := ctrl;      -- accept new control settings at end of block when gapsize=0
-            v.samples_cnt := 0; 
-            v.blocks_cnt  := r.blocks_cnt + 1;
-          elsif r.samples_cnt >= v_samples_per_packet-1 then 
-            v.eop         := '1'; 
-            v.samples_cnt := 0; 
-            v.rd_ena      := '0';
-            v.state       := s_gap;
-          else 
-            v.samples_cnt := r.samples_cnt + 1;
-          end if;
-          v.valid  := '1';
+          if out_siso.ready='1' then
           
-          if r.mem_cnt >= v_mem_high_adrs then 
-            v.mem_cnt := v_mem_low_adrs;
-          else
-            v.mem_cnt := r.mem_cnt + 1;
-          end if; 
+            v.rd_ena := '1';  -- read next data
+            if r.samples_cnt = 0 and r.blocks_cnt = 0 then 
+              v.pls_sync    := '1';                      -- Always start with a pulse sync          
+              v.blk_sync    := '1';
+              v.sop         := '1';
+              v.samples_cnt := v.samples_cnt + 1; 
+            elsif r.samples_cnt = 0 then
+              v.sop         := '1';
+              v.samples_cnt := v.samples_cnt + 1; 
+            elsif r.samples_cnt >= v_samples_per_packet-1 and v_gapsize = 0 and r.blocks_cnt >= v_blocks_per_sync-1 then 
+              v.eop         := '1'; 
+              v.ctrl_reg    := ctrl;      -- accept new control settings at end of block when gapsize=0
+              v.samples_cnt := 0; 
+              v.blocks_cnt  := 0;
+            elsif r.samples_cnt >= v_samples_per_packet-1 and v_gapsize = 0 then 
+              v.eop         := '1'; 
+              v.ctrl_reg    := ctrl;      -- accept new control settings at end of block when gapsize=0
+              v.samples_cnt := 0; 
+              v.blocks_cnt  := r.blocks_cnt + 1;
+            elsif r.samples_cnt >= v_samples_per_packet-1 then 
+              v.eop         := '1'; 
+              v.samples_cnt := 0; 
+              v.rd_ena      := '0';
+              v.state       := s_gap;
+            else 
+              v.samples_cnt := r.samples_cnt + 1;
+            end if;
+            v.valid  := '1';  -- output pending data
+            
+            if r.mem_cnt >= v_mem_high_adrs then 
+              v.mem_cnt := v_mem_low_adrs;
+            else
+              v.mem_cnt := r.mem_cnt + 1;
+            end if; 
+            
+            if v.eop = '1' and r.blk_en = '0' then
+              v.state := s_idle;          -- accept disable after eop, not during block
+            end if;
+            if r.eop = '1' then
+              v.blk_xon := out_siso.xon;  -- accept XOFF after eop, not during block
+            end if;
           
-          if v.eop = '1' and r.blk_en = '0' then
-            v.state := s_idle;          -- accept disable after eop, not during block
-          end if;
-          if r.eop = '1' then
-            v.blk_xon := out_siso.xon;  -- accept XOFF after eop, not during block
-          end if;
+          end if;  -- out_siso.ready='1'
 
         when s_gap => 
           if r.samples_cnt >= v_gapsize-1 and r.blocks_cnt >= v_blocks_per_sync-1 then