Correct using g_use_dp_latency_adapter.

libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd

@@ -58,7 +58,7 @@
 --     src_in.ready is used registered.
 --   . The p_reg increases the ready latency (RL) by 1, because p_comb does
 --     not use src_in.ready, instead p_comb drives d.src_out based on the
---     snk_in.sop, eop, valid. Therefore c_use_dp_latency_adapter = true is
+--     snk_in.sop, eop, valid. Therefore g_use_dp_latency_adapter = true is
 --     needed to restore the RL from 2 to 1 for the src_out the output. The
 --     alternative is to use a dp_pipeline to register d.src_out in
 --     combination with src_in.ready at the input, to keep RL at 1.
@@ -103,14 +103,10 @@ architecture rtl of dp_packet_unmerge is
 
   constant c_reg_rst : t_reg := (0, 0, c_dp_sosi_rst);
 
-  constant c_use_dp_latency_adapter : boolean := false;
-
   signal r : t_reg;
   signal d : t_reg;
 
-  -- Signals for c_use_dp_latency_adapter = false
-
-  -- Signals for c_use_dp_latency_adapter = true
+  -- Signals for g_use_dp_latency_adapter = true
   signal dp_latency_adapter_snk_out : t_dp_siso;
   signal dp_latency_adapter_snk_in  : t_dp_sosi;
   signal dp_latency_adapter_src_in  : t_dp_siso;
@@ -123,7 +119,7 @@ begin
   end generate;
 
   gen_use_src_in_ready : if g_use_src_in_ready = true generate
-    gen_dp_pipeline : if c_use_dp_latency_adapter = false generate
+    gen_dp_pipeline : if g_use_dp_latency_adapter = false generate
       u_dp_pipeline : entity work.dp_pipeline
       port map (
         rst          => rst,
@@ -137,7 +133,7 @@ begin
       );
     end generate;
 
-    gen_dp_latency_adapter : if c_use_dp_latency_adapter = true generate
+    gen_dp_latency_adapter : if g_use_dp_latency_adapter = true generate
       snk_out <= dp_latency_adapter_snk_out;
       dp_latency_adapter_snk_in <= r.src_out;