corrected number of pipeline stages

libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd

@@ -60,7 +60,7 @@ ARCHITECTURE rtl of nw_ping_response IS
   CONSTANT c_dp_fifo_size    : NATURAL := 16;
 
   CONSTANT c_cin_w : NATURAL := 4;
-  CONSTANT c_pipeline : NATURAL := c_network_total_header_64b_nof_words + 5; -- Header length and 5 more pipeline cycles to allow for the other states
+  CONSTANT c_pipeline : NATURAL := c_network_total_header_64b_nof_words + 3; -- Header length and 3 more pipeline cycles to allow for the other states
 
   TYPE t_state IS (s_idle, s_capture, s_check, s_sum, s_output, s_wait);
   
@@ -164,18 +164,14 @@ BEGIN
             v.src_out.data(c_halfword_w*4 -1 DOWNTO c_halfword_w *3) := r.ip_checksum;
           ELSIF r.word_cnt = 4 THEN -- insert icmp checksum
             v.src_out.data(c_halfword_w*2 -1 DOWNTO c_halfword_w) := r.icmp_checksum;
-          END IF;
-   
-          IF dp_pipeline_src_out.eop = '1' THEN
+          ELSIF dp_pipeline_src_out.eop = '1' THEN
             v.state := s_wait;
           END IF;
         END IF;
 
       WHEN s_wait =>
-            v.src_out.valid := '0';
-            v.src_out.sop := '0';
-            v.src_out.eop := '0';          
-        IF dp_fifo_sc_rd_emp = '1' THEN -- Wait until ping respose has left the fifo
+            v.src_out := c_dp_sosi_rst;
+        IF dp_fifo_sc_rd_emp = '1' THEN -- Wait until ping response has left the fifo
           v := c_r_rst;
         END IF;