Added MM broadcast access option.

libraries/base/common/src/vhdl/common_mem_mux.vhd

@@ -42,6 +42,11 @@
 --        . not selected mosi_arr get mosi but with wr='0', rd='0'
 --        . not selected miso_arr are ignored
 --
+--   Use default g_broadcast=FALSE for multiplexed individual MM access to
+--   each mosi_arr/miso_arr MM port. When g_broadcast=TRUE then a write
+--   access to MM port [0] is passed on to all ports and a read access is
+--   done from MM port [0]. The other ports cannot be read.
+--
 -- Remarks:
 -- . In simulation selecting an unused element address will cause a simulation
 --   failure. Therefore the element index is only accepted when it is in the
@@ -58,7 +63,8 @@ USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 
 ENTITY common_mem_mux IS
-  GENERIC (    
+  GENERIC (
+    g_broadcast   : BOOLEAN := FALSE;
     g_nof_mosi    : POSITIVE := 256;     -- Number of memory interfaces in the array.
     g_mult_addr_w : POSITIVE := 8;       -- Address width of each memory-interface element in the muliplexed array.
     g_rd_latency  : NATURAL := 0
@@ -83,12 +89,12 @@ ARCHITECTURE rtl OF common_mem_mux IS
 
 BEGIN
 
-  gen_single : IF g_nof_mosi=1 GENERATE 
+  gen_single : IF g_broadcast=FALSE AND g_nof_mosi=1 GENERATE 
     mosi_arr(0) <= mosi;
     miso        <= miso_arr(0);
   END GENERATE;
     
-  gen_multiple : IF g_nof_mosi>1 GENERATE 
+  gen_multiple : IF g_broadcast=FALSE AND g_nof_mosi>1 GENERATE 
     -- The activated element of the array is detected here
     index_arr(0) <= TO_UINT(mosi.address(c_total_addr_w-1 DOWNTO g_mult_addr_w));
 
@@ -129,4 +135,9 @@ BEGIN
     END PROCESS;
   END GENERATE; 
   
+  gen_broadcast : IF g_broadcast=TRUE GENERATE
+    mosi_arr <= (OTHERS=>mosi);  -- broadcast write to all [g_nof_mosi-1:0] MM ports
+    miso     <= miso_arr(0);     -- broadcast read only from MM port [0]
+  END GENERATE;
+  
 END rtl;