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Commit aade3318 authored by Eric Kooistra's avatar Eric Kooistra
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Use dp_stimuli_st and dp_verify_st in tb_dp_example_no_dut.

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libraries/base/dp/tb/vhdl/dp_stimuli_st.vhd
+ 24
− 33
View file @ aade3318
......@@ -39,15 +39,23 @@ USE work.tb_dp_pkg.ALL;
ENTITY dp_stimuli_st IS
GENERIC (
-- general
g_index : NATURAL := 0;
g_instance_nr : NATURAL := 0;
-- flow control
g_random_w : NATURAL := 15; -- use different random width for stimuli and for verify to have different random sequences
g_flow_control : t_dp_flow_control_enum := e_pulse; -- always active, random or pulse flow control
g_pulse_active : NATURAL := 1;
g_pulse_period : NATURAL := 2;
g_flow_control : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
-- initializations
g_sync_period : NATURAL := 10;
g_sync_offset : NATURAL := 7;
g_data_init : INTEGER := -1;
g_bsn_init : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := X"0000000000000000"; -- X"0877665544332211"
g_err_init : NATURAL := 247;
g_channel_init : INTEGER := 5; -- fixed
-- specific
g_in_dat_w : NATURAL := 32;
g_in_nof_words : NATURAL := 1;
g_nof_repeat : NATURAL := 5;
g_pkt_len : NATURAL := 16; -- must be a multiple of g_in_nof_words
g_pkt_len : NATURAL := 16;
g_pkt_gap : NATURAL := 4
);
PORT (
......@@ -67,19 +75,8 @@ END dp_stimuli_st;
ARCHITECTURE str OF dp_stimuli_st IS
CONSTANT c_pulse_active : NATURAL := g_in_nof_words;
CONSTANT c_pulse_period : NATURAL := g_in_nof_words;
CONSTANT c_sync_period : NATURAL := 10;
CONSTANT c_sync_offset : NATURAL := 7;
CONSTANT c_data_init : INTEGER := -1;
CONSTANT c_bsn_init : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := X"0000000000000000"; -- X"0877665544332211"
CONSTANT c_err_init : NATURAL := 247;
CONSTANT c_channel_init : INTEGER := 5; -- fixed
SIGNAL random : STD_LOGIC_VECTOR(g_random_w-1 DOWNTO 0) := TO_UVEC(g_index, g_random_w); -- use different initialization to have different random sequences per stream
SIGNAL random : STD_LOGIC_VECTOR(g_random_w-1 DOWNTO 0) := TO_UVEC(g_instance_nr, g_random_w); -- use different initialization to have different random sequences per stream
SIGNAL pulse : STD_LOGIC;
SIGNAL pulse_en : STD_LOGIC := '1';
......@@ -87,19 +84,13 @@ ARCHITECTURE str OF dp_stimuli_st IS
SIGNAL stimuli_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL i_stimuli_src_out : t_dp_sosi;
SIGNAL dut_snk_out : t_dp_siso;
SIGNAL dut_snk_in : t_dp_sosi;
SIGNAL dut_src_in : t_dp_siso;
SIGNAL dut_src_out : t_dp_sosi;
BEGIN
stimuli_src_out <= i_stimuli_src_out;
random <= func_common_random(random) WHEN rising_edge(clk);
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period, '1', rst, clk, pulse_en, pulse);
proc_common_gen_duty_pulse(g_pulse_active, g_pulse_period, '1', rst, clk, pulse_en, pulse);
------------------------------------------------------------------------------
-- STREAM CONTROL
......@@ -123,20 +114,20 @@ BEGIN
tb_end <= '0';
-- Adjust initial sosi field values by -1 to compensate for auto increment
v_sosi.bsn := INCR_UVEC(c_bsn_init, -1);
v_sosi.channel := INCR_UVEC(TO_DP_CHANNEL(c_channel_init), -1);
v_sosi.data := INCR_UVEC(TO_DP_DATA(c_data_init), -1);
v_sosi.err := INCR_UVEC(TO_DP_ERROR(c_err_init), -1);
v_sosi.bsn := INCR_UVEC(g_bsn_init, -1);
v_sosi.channel := INCR_UVEC(TO_DP_CHANNEL(g_channel_init), -1);
v_sosi.data := INCR_UVEC(TO_DP_DATA(g_data_init), -1);
v_sosi.err := INCR_UVEC(TO_DP_ERROR(g_err_init), -1);
i_stimuli_src_out <= c_dp_sosi_rst;
proc_common_wait_until_low(clk, rst);
proc_common_wait_some_cycles(clk, 5);
-- Generate c_nof_repeat packets
-- Generate g_nof_repeat packets
FOR I IN 0 TO g_nof_repeat-1 LOOP
-- Auto increment v_sosi field values for this packet
v_sosi.bsn := INCR_UVEC(v_sosi.bsn, 1);
v_sosi.sync := sel_a_b((UNSIGNED(v_sosi.bsn) MOD c_sync_period) = c_sync_offset, '1', '0'); -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
v_sosi.sync := sel_a_b((UNSIGNED(v_sosi.bsn) MOD g_sync_period) = g_sync_offset, '1', '0'); -- insert sync starting at BSN=g_sync_offset and with period g_sync_period
v_sosi.channel := INCR_UVEC(v_sosi.channel, 1);
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len);
v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w-1 DOWNTO 0)); -- wrap when >= 2**g_in_dat_w
......@@ -151,9 +142,9 @@ BEGIN
-- Determine expected sosi field values after end of stimuli
-- . e_qual
v_sosi.bsn := STD_LOGIC_VECTOR( UNSIGNED(c_bsn_init) + g_nof_repeat-1);
v_sosi.channel := TO_DP_CHANNEL(c_channel_init + g_nof_repeat-1);
v_sosi.err := TO_DP_ERROR(c_err_init + g_nof_repeat-1);
v_sosi.bsn := STD_LOGIC_VECTOR( UNSIGNED(g_bsn_init) + g_nof_repeat-1);
v_sosi.channel := TO_DP_CHANNEL(g_channel_init + g_nof_repeat-1);
v_sosi.err := TO_DP_ERROR(g_err_init + g_nof_repeat-1);
-- . account for g_pkt_len
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len-1);
v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w-1 DOWNTO 0)); -- wrap when >= 2**g_in_dat_w
......
libraries/base/dp/tb/vhdl/dp_verify_st.vhd
+ 14
− 17
View file @ aade3318
......@@ -51,7 +51,7 @@ ENTITY dp_verify_st IS
g_sync_offset : NATURAL := 7;
-- specific
g_in_dat_w : NATURAL := 32;
g_pkt_len : NATURAL := 16;
g_pkt_len : NATURAL := 16
);
PORT (
rst : IN STD_LOGIC;
......@@ -63,8 +63,7 @@ ENTITY dp_verify_st IS
-- End of stimuli
expected_verify_snk_in : IN t_dp_sosi; -- expected verify_snk_in after end of stimuli
verify_last : IN STD_LOGIC; -- trigger verify to verify the expected_verify_snk_in
tb_end : IN STD_LOGIC -- signal end of tb as far as this dp_stimuli_st is concerned
verify_last : IN STD_LOGIC -- trigger verify to verify the expected_verify_snk_in
);
END dp_verify_st;
......@@ -76,18 +75,14 @@ ARCHITECTURE tb OF dp_verify_st IS
CONSTANT c_data_max : UNSIGNED(g_in_dat_w-1 DOWNTO 0) := (OTHERS=>'1');
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC := '1';
SIGNAL sl1 : STD_LOGIC := '1';
SIGNAL random : STD_LOGIC_VECTOR(g_random_w-1 DOWNTO 0) := TO_UVEC(g_instance_nr, g_random_w); -- use different initialization to have different random sequences per stream
SIGNAL pulse : STD_LOGIC;
SIGNAL pulse_en : STD_LOGIC := '1';
SIGNAL i_verify_snk_out : t_dp_siso := c_dp_siso_rdy;
SIGNAL prev_verify_snk_out : t_dp_siso;
SIGNAL verify_snk_out : t_dp_siso := c_dp_siso_rdy;
SIGNAL verify_snk_in : t_dp_sosi;
SIGNAL verify_snk_in_data : STD_LOGIC_VECTOR(c_dp_stream_data_w-1 DOWNTO 0); -- used to hold valid data for verify at verify_last
SIGNAL verify_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL prev_verify_snk_in : t_dp_sosi;
......@@ -102,11 +97,13 @@ ARCHITECTURE tb OF dp_verify_st IS
BEGIN
verify_snk_out <= i_verify_snk_out;
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
random_1 <= func_common_random(random_1) WHEN rising_edge(clk);
random <= func_common_random(random) WHEN rising_edge(clk);
proc_common_gen_duty_pulse(g_pulse_active, g_pulse_period, '1', rst, clk, pulse_en, pulse);
......@@ -114,9 +111,9 @@ BEGIN
-- STREAM CONTROL
------------------------------------------------------------------------------
verify_snk_out.ready <= '1' WHEN g_flow_control=e_active ELSE
random(random'HIGH) WHEN g_flow_control=e_random ELSE
pulse WHEN g_flow_control=e_pulse;
i_verify_snk_out.ready <= '1' WHEN g_flow_control=e_active ELSE
random(random'HIGH) WHEN g_flow_control=e_random ELSE
pulse WHEN g_flow_control=e_pulse;
-- Start verify after first valid, sop or eop
......@@ -134,10 +131,10 @@ BEGIN
--proc_dp_verify_value("verify_snk_in.err", e_equal, clk, verify_last, expected_verify_snk_in.err, verify_snk_in.err);
-- Verify that the output is incrementing data, like the input stimuli
proc_dp_verify_data("verify_snk_in.data", c_rl, c_data_max, c_unsigned_1, clk, verify_en_valid, verify_snk_out.ready, verify_snk_in.valid, verify_snk_in.data, prev_verify_snk_in.data);
--proc_dp_verify_data("verify_snk_in.bsn", c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_sop, verify_snk_out.ready, verify_snk_in.sop, verify_snk_in.bsn, prev_verify_snk_in.bsn);
--proc_dp_verify_data("verify_snk_in.channel", c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_sop, verify_snk_out.ready, verify_snk_in.sop, verify_snk_in.channel, prev_verify_snk_in.channel);
--proc_dp_verify_data("verify_snk_in.err", c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_eop, verify_snk_out.ready, verify_snk_in.eop, verify_snk_in.err, prev_verify_snk_in.err);
proc_dp_verify_data("verify_snk_in.data", c_rl, c_data_max, c_unsigned_1, clk, verify_en_valid, i_verify_snk_out.ready, verify_snk_in.valid, verify_snk_in.data, prev_verify_snk_in.data);
--proc_dp_verify_data("verify_snk_in.bsn", c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_sop, i_verify_snk_out.ready, verify_snk_in.sop, verify_snk_in.bsn, prev_verify_snk_in.bsn);
--proc_dp_verify_data("verify_snk_in.channel", c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_sop, i_verify_snk_out.ready, verify_snk_in.sop, verify_snk_in.channel, prev_verify_snk_in.channel);
--proc_dp_verify_data("verify_snk_in.err", c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_eop, i_verify_snk_out.ready, verify_snk_in.eop, verify_snk_in.err, prev_verify_snk_in.err);
-- Verify that the output sync occurs when expected
--proc_dp_verify_sync(g_sync_period, g_sync_offset, clk, verify_en_sop, verify_snk_in.sync, verify_snk_in.sop, verify_snk_in.bsn);
......@@ -151,7 +148,7 @@ BEGIN
proc_dp_verify_block_size(exp_size, clk, verify_snk_in.valid, verify_snk_in.sop, verify_snk_in.eop, cnt_size);
-- Verify output ready latency
proc_dp_verify_valid(clk, verify_en_valid, verify_snk_out.ready, prev_verify_snk_out.ready, verify_snk_in.valid);
proc_dp_verify_valid(clk, verify_en_valid, i_verify_snk_out.ready, prev_verify_snk_out.ready, verify_snk_in.valid);
------------------------------------------------------------------------------
-- Auxiliary
......
libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
+ 43
− 65
View file @ aade3318
......@@ -127,9 +127,8 @@ ENTITY tb_dp_example_no_dut IS
g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
-- specific
g_in_dat_w : NATURAL := 32;
g_in_nof_words : NATURAL := 1;
g_nof_repeat : NATURAL := 5;
g_pkt_len : NATURAL := 16; -- must be a multiple of g_in_nof_words
g_pkt_len : NATURAL := 16;
g_pkt_gap : NATURAL := 4
);
END tb_dp_example_no_dut;
......@@ -137,15 +136,16 @@ END tb_dp_example_no_dut;
ARCHITECTURE tb OF tb_dp_example_no_dut IS
CONSTANT c_rl : NATURAL := 1;
CONSTANT c_no_dut : BOOLEAN:= TRUE;
CONSTANT c_stimuli_pulse_active : NATURAL := 1;
CONSTANT c_stimuli_pulse_period : NATURAL := 2;
CONSTANT c_pulse_active : NATURAL := g_in_nof_words;
CONSTANT c_pulse_period : NATURAL := g_in_nof_words;
CONSTANT c_verify_pulse_active : NATURAL := 1;
CONSTANT c_verify_pulse_period : NATURAL := 2;
CONSTANT c_sync_period : NATURAL := 10;
CONSTANT c_sync_offset : NATURAL := 7;
CONSTANT c_data_max : UNSIGNED(g_in_dat_w-1 DOWNTO 0) := (OTHERS=>'1');
CONSTANT c_data_init : INTEGER := -1;
CONSTANT c_bsn_init : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := X"0000000000000000"; -- X"0877665544332211"
......@@ -155,11 +155,6 @@ ARCHITECTURE tb OF tb_dp_example_no_dut IS
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC := '1';
SIGNAL sl1 : STD_LOGIC := '1';
SIGNAL random_1 : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences
SIGNAL pulse_1 : STD_LOGIC;
SIGNAL pulse_en : STD_LOGIC := '1';
SIGNAL stimuli_src_in : t_dp_siso;
SIGNAL stimuli_src_out : t_dp_sosi;
......@@ -171,17 +166,11 @@ ARCHITECTURE tb OF tb_dp_example_no_dut IS
SIGNAL dut_src_in : t_dp_siso;
SIGNAL dut_src_out : t_dp_sosi;
SIGNAL prev_verify_snk_out : t_dp_siso;
SIGNAL verify_snk_out : t_dp_siso := c_dp_siso_rdy;
SIGNAL verify_snk_in : t_dp_sosi;
SIGNAL verify_snk_in_data : STD_LOGIC_VECTOR(c_dp_stream_data_w-1 DOWNTO 0); -- used to hold valid data for verify at verify_last
SIGNAL verify_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL prev_verify_snk_in : t_dp_sosi;
SIGNAL verify_hold_sop : STD_LOGIC := '0';
SIGNAL verify_en_valid : STD_LOGIC := '0';
SIGNAL verify_en_sop : STD_LOGIC := '0';
SIGNAL verify_en_eop : STD_LOGIC := '0';
SIGNAL verify_last : STD_LOGIC := '0';
SIGNAL expected_verify_snk_in : t_dp_sosi;
......@@ -199,13 +188,21 @@ BEGIN
u_dp_stimuli_st : ENTITY work.dp_stimuli_st
GENERIC MAP (
-- general
g_index => 0, -- only one stream so choose index 0
g_instance_nr => 0, -- only one stream so choose index 0
-- flow control
g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
g_pulse_active => c_stimuli_pulse_active,
g_pulse_period => c_stimuli_pulse_period,
g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
g_data_init => c_data_init,
g_bsn_init => c_bsn_init,
g_err_init => c_err_init,
g_channel_init => c_channel_init,
-- specific
g_in_dat_w => g_in_dat_w,
g_in_nof_words => g_in_nof_words,
g_nof_repeat => g_nof_repeat,
g_pkt_len => g_pkt_len,
g_pkt_gap => g_pkt_gap
......@@ -229,53 +226,33 @@ BEGIN
-- DATA VERIFICATION
------------------------------------------------------------------------------
random_1 <= func_common_random(random_1) WHEN rising_edge(clk);
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period+1, '1', rst, clk, pulse_en, pulse_1);
------------------------------------------------------------------------------
-- STREAM CONTROL
------------------------------------------------------------------------------
verify_snk_out.ready <= '1' WHEN g_flow_control_verify=e_active ELSE
random_1(random_1'HIGH) WHEN g_flow_control_verify=e_random ELSE
pulse_1 WHEN g_flow_control_verify=e_pulse;
-- Start verify after first valid, sop or eop
verify_en_valid <= '1' WHEN verify_snk_in.valid='1' AND rising_edge(clk);
verify_en_sop <= '1' WHEN verify_snk_in.sop='1' AND rising_edge(clk);
verify_en_eop <= '1' WHEN verify_snk_in.eop='1' AND rising_edge(clk);
-- Verify that the stimuli have been applied at all
proc_dp_verify_value("verify_snk_in.valid", clk, verify_last, sl1, verify_en_valid);
proc_dp_verify_value("verify_snk_in.sop", clk, verify_last, sl1, verify_en_sop);
proc_dp_verify_value("verify_snk_in.eop", clk, verify_last, sl1, verify_en_eop);
proc_dp_verify_value("verify_snk_in.data", e_equal, clk, verify_last, expected_verify_snk_in.data, verify_snk_in_data);
--proc_dp_verify_value("verify_snk_in.bsn", e_equal, clk, verify_last, expected_verify_snk_in.bsn, verify_snk_in.bsn);
--proc_dp_verify_value("verify_snk_in.channel", e_equal, clk, verify_last, expected_verify_snk_in.channel, verify_snk_in.channel);
--proc_dp_verify_value("verify_snk_in.err", e_equal, clk, verify_last, expected_verify_snk_in.err, verify_snk_in.err);
-- Verify that the output is incrementing data, like the input stimuli
proc_dp_verify_data("verify_snk_in.data", c_rl, c_data_max, c_unsigned_1, clk, verify_en_valid, verify_snk_out.ready, verify_snk_in.valid, verify_snk_in.data, prev_verify_snk_in.data);
--proc_dp_verify_data("verify_snk_in.bsn", c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_sop, verify_snk_out.ready, verify_snk_in.sop, verify_snk_in.bsn, prev_verify_snk_in.bsn);
--proc_dp_verify_data("verify_snk_in.channel", c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_sop, verify_snk_out.ready, verify_snk_in.sop, verify_snk_in.channel, prev_verify_snk_in.channel);
--proc_dp_verify_data("verify_snk_in.err", c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_eop, verify_snk_out.ready, verify_snk_in.eop, verify_snk_in.err, prev_verify_snk_in.err);
-- Verify that the output sync occurs when expected
--proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_en_sop, verify_snk_in.sync, verify_snk_in.sop, verify_snk_in.bsn);
-- Verify output packet ctrl
proc_dp_verify_sop_and_eop(clk, verify_snk_in.valid, verify_snk_in.sop, verify_snk_in.eop, verify_hold_sop);
-- Verify output packet block size
exp_size <= g_pkt_len;
u_dp_verify_st : ENTITY work.dp_verify_st
GENERIC MAP (
g_instance_nr => 0, -- only one stream so choose index 0
-- flow control
g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
g_pulse_active => c_verify_pulse_active,
g_pulse_period => c_verify_pulse_period,
g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
-- specific
g_in_dat_w => g_in_dat_w,
g_pkt_len => g_pkt_len
)
PORT MAP (
rst => rst,
clk => clk,
proc_dp_verify_block_size(exp_size, clk, verify_snk_in.valid, verify_snk_in.sop, verify_snk_in.eop, cnt_size);
-- Verify data
verify_snk_out => verify_snk_out,
verify_snk_in => verify_snk_in,
-- Verify output ready latency
proc_dp_verify_valid(clk, verify_en_valid, verify_snk_out.ready, prev_verify_snk_out.ready, verify_snk_in.valid);
-- End of stimuli
expected_verify_snk_in => expected_verify_snk_in, -- expected verify_snk_in after end of stimuli
verify_last => verify_last -- trigger verify to verify the expected_verify_snk_in
);
------------------------------------------------------------------------------
-- DUT
......@@ -309,4 +286,5 @@ BEGIN
verify_data <= verify_snk_in.data(g_in_dat_w-1 DOWNTO 0);
verify_snk_in_data <= verify_snk_in.data WHEN verify_snk_in.valid='1';
END tb;
libraries/base/dp/tb/vhdl/tb_tb_dp_example_no_dut.vhd
+ 5
− 6
View file @ aade3318
......@@ -45,14 +45,13 @@ BEGIN
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
-- -- specific
-- g_in_dat_w : NATURAL := 32;
-- g_in_nof_words : NATURAL := 1;
-- g_nof_repeat : NATURAL := 5;
-- g_pkt_len : NATURAL := 16; -- must be a multiple of g_in_nof_words
-- g_pkt_len : NATURAL := 16;
-- g_pkt_gap : NATURAL := 4
u_act_act : ENTITY work.tb_dp_example_no_dut GENERIC MAP ( e_active, e_active, 16, 1, c_nof_repeat, 16, 4);
u_rnd_act : ENTITY work.tb_dp_example_no_dut GENERIC MAP ( e_random, e_active, 16, 1, c_nof_repeat, 16, 4);
u_rnd_rnd : ENTITY work.tb_dp_example_no_dut GENERIC MAP ( e_random, e_random, 16, 1, c_nof_repeat, 16, 4);
u_pls_pls : ENTITY work.tb_dp_example_no_dut GENERIC MAP ( e_pulse, e_pulse, 16, 1, c_nof_repeat, 16, 4);
u_act_act : ENTITY work.tb_dp_example_no_dut GENERIC MAP ( e_active, e_active, 16, c_nof_repeat, 16, 4);
u_rnd_act : ENTITY work.tb_dp_example_no_dut GENERIC MAP ( e_random, e_active, 16, c_nof_repeat, 16, 4);
u_rnd_rnd : ENTITY work.tb_dp_example_no_dut GENERIC MAP ( e_random, e_random, 16, c_nof_repeat, 16, 4);
u_pls_pls : ENTITY work.tb_dp_example_no_dut GENERIC MAP ( e_pulse, e_pulse, 16, c_nof_repeat, 16, 4);
END tb;
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