Corrected use of c_wb_fifo_fill_level. Use condition b) for...

Corrected use of c_wb_fifo_fill_level. Use condition b) for dp_phs_align_restart instead of condition a).

libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd

@@ -174,13 +174,13 @@ ARCHITECTURE str OF lvdsh_dd_phs4 IS
   
   CONSTANT c_wb_sync_period         : NATURAL := g_dp_phs_clk_period;       -- nof dp_clk cycles for wb_sync period, must be > c_wb_sync_roundtrip
   CONSTANT c_wb_cnt_w               : NATURAL := ceil_log2(c_wb_sync_period);
-  CONSTANT c_wb_fifo_fill_offset    : INTEGER := 2;         -- some offset to adjust the mean fifo fill level
-  CONSTANT c_wb_sync_in_latency     : NATURAL := 12;        -- estimated nof dp_clk cycles latency of wb_sync transfer in the in_clk domain based on simulation and measurement on hardware
-  CONSTANT c_wb_sync_roundtrip      : NATURAL := c_wb_fifo_fill_offset+g_dp_phs_clk_period/2;  -- achieve this nof dp_clk cycles from getting wb_sync back via dp_sync
+  CONSTANT c_wb_sync_in_latency     : NATURAL := 5;    -- estimated nof dp_clk cycles latency of wb_sync transfer from dp_clk to in_clk domain and the latency in lvdsh_dd_phs4_align
+  CONSTANT c_wb_fifo_fill_latency   : NATURAL := 5;    -- estimated nof dp_clk cycles latency of fifo_rdusedw - fifo_wrused
+  CONSTANT c_wb_fifo_fill_level     : INTEGER := 12;    -- set expected FIFO fill level on read side  (mean level +- 1 can occur)
+  CONSTANT c_wb_sync_roundtrip        : NATURAL := c_wb_sync_in_latency+c_wb_fifo_fill_latency+c_wb_fifo_fill_level;  -- achieve this nof dp_clk cycles from getting wb_sync back via dp_sync
   CONSTANT c_wb_sync_roundtrip_margin : NATURAL := 2;
   CONSTANT c_wb_sync_roundtrip_max    : NATURAL := c_wb_sync_roundtrip+c_wb_sync_roundtrip_margin;
   CONSTANT c_wb_sync_roundtrip_min    : NATURAL := c_wb_sync_roundtrip-c_wb_sync_roundtrip_margin;
-  CONSTANT c_wb_fifo_fill_level     : NATURAL := c_wb_fifo_fill_offset+c_wb_sync_roundtrip-c_wb_sync_in_latency;  -- expected FIFO fill level on read side  (mean level +- 1 can occur),
   CONSTANT c_wb_fifo_fill_margin    : NATURAL := 2;                         -- some symmetrical FIFO filled margin >= 0, use 0 in theory, use 1 to allow some timing uncertainty in rdusedw of dual clock FIFO
   CONSTANT c_wb_fifo_fill_margin_p  : NATURAL := c_wb_fifo_fill_margin;     -- some FIFO more filled margin >= 0, use 0 or 1 to allow 8 and 9
   CONSTANT c_wb_fifo_fill_margin_n  : NATURAL := c_wb_fifo_fill_margin;     -- some FIFO less filled margin >= 0, use 1 or 2 to allow 7 and 6
@@ -190,12 +190,14 @@ ARCHITECTURE str OF lvdsh_dd_phs4 IS
   -- view debug signals in Wave Window
   SIGNAL dbg_c_dp_phs_align_en      : BOOLEAN := c_dp_phs_align_en;
   SIGNAL dbg_c_wb_sync_period       : NATURAL := c_wb_sync_period;
-  SIGNAL dbg_c_wb_fifo_fill_offset  : INTEGER := c_wb_fifo_fill_offset;
   SIGNAL dbg_c_wb_sync_in_latency   : NATURAL := c_wb_sync_in_latency;
-  SIGNAL dbg_c_wb_sync_roundtrip    : NATURAL := c_wb_sync_roundtrip;
+  SIGNAL dbg_c_wb_fifo_fill_latency : NATURAL := c_wb_fifo_fill_latency;
   SIGNAL dbg_c_wb_fifo_fill_max     : NATURAL := c_wb_fifo_fill_max;
   SIGNAL dbg_c_wb_fifo_fill_level   : NATURAL := c_wb_fifo_fill_level;  -- must be > c_word_req_lat to ensure that fifo_rdusedw > 0
   SIGNAL dbg_c_wb_fifo_fill_min     : NATURAL := c_wb_fifo_fill_min;
+  SIGNAL dbg_c_wb_sync_roundtrip    : NATURAL := c_wb_sync_roundtrip;
+  SIGNAL dbg_c_wb_sync_roundtrip_max: NATURAL := c_wb_sync_roundtrip_max;
+  SIGNAL dbg_c_wb_sync_roundtrip_min: NATURAL := c_wb_sync_roundtrip_min;
   
   SIGNAL dbg_status_0_out_word_locked       : STD_LOGIC;
   SIGNAL dbg_status_1_out_word_stable       : STD_LOGIC;
@@ -326,7 +328,9 @@ BEGIN
   --    no longer occur, because the lvdsh_dd_phs4_align then continues on the current phs using common_toggle_align.
   --    The dp_word_lock_failed can still occur, but only if the course check on wb_cnt_roundtrip latency and fifo_rdusedw FIFO fill 
   --    level fails by more than a +-1 margin. 
-  dp_phs_align_restart <= dp_phs_timeout OR dp_phs_lock_lost OR r_dp.dp_word_lock_failed;
+  --dp_phs_align_restart <= dp_phs_timeout OR dp_phs_lock_lost OR r_dp.dp_word_lock_failed;     -- a) should be robust enough to never detect loss lock as long as in_clk stays active
+  dp_phs_align_restart <= dp_phs_timeout OR dp_phs_lock_lost OR (r_dp.dp_word_lock_failed AND NOT r_dp.dp_maintain_phs);    -- b) even a bit stronger then a)
+  --dp_phs_align_restart <= (dp_phs_timeout OR dp_phs_lock_lost OR r_dp.dp_word_lock_failed) AND (NOT r_dp.dp_maintain_phs);     -- c) is equivalent to b) so should not make a difference
   
   -- Extend dp_phs_align_restart to filter out any subsequent restart triggers
   u_common_pulse_extend : ENTITY common_lib.common_pulse_extend