Ported mms_diag_block_gen.vhd to RadioHDL (no changes yet).

Added tb_diag_regression.vhd.

libraries/base/diag/hdllib.cfg

@@ -28,7 +28,7 @@ synth_files =
     $UNB/Firmware/modules/Lofar/diag/src/vhdl/mms_diag_data_buffer.vhd
     $UNB/Firmware/modules/Lofar/diag/src/vhdl/diag_block_gen.vhd
     $UNB/Firmware/modules/Lofar/diag/src/vhdl/diag_block_gen_reg.vhd
-    $UNB/Firmware/modules/Lofar/diag/src/vhdl/mms_diag_block_gen.vhd
+    src/vhdl/mms_diag_block_gen.vhd
 
 test_bench_files = 
     $UNB/Firmware/modules/Lofar/diag/tb/vhdl/tb_diag_wg.vhd
@@ -41,3 +41,4 @@ test_bench_files =
     $UNB/Firmware/modules/Lofar/diag/tb/vhdl/tb_diag_frm_monitor.vhd
     $UNB/Firmware/modules/Lofar/diag/tb/vhdl/tb_mms_diag_seq.vhd
     $UNB/Firmware/modules/Lofar/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
+    tb/vhdl/tb_diag_regression.vhd

libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Block generator for multiple parallel SOSI streams
+-- Description:
+-- . The mms_diag_block_gen provides a MM slave interface to an array of
+--   g_nof_output_streams diag_block_gen instances.
+-- . The waveform data is stored in RAM and can be pre-load with data from a
+--   file g_file_name_prefix. The stream index to the select the actual file
+--   is default I, but can be set via g_file_index_arr(I). The g_file_index_arr
+--   makes the relation between the instance index and file index flexible.
+-- Remark:
+-- . The diag_block_gen does not support back pressure, but it does support
+--   XON/XOFF flow control at block level via out_siso.xon.
+-- . Default input *_mosi = c_mem_mosi_rst to support using the BG with default
+--   control and memory settings and no MM interface
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL; 
+USE work.diag_pkg.ALL;
+
+ENTITY mms_diag_block_gen IS
+  GENERIC (    
+    g_blk_sync           : BOOLEAN := FALSE;
+    g_nof_output_streams : POSITIVE := 16;
+    g_buf_dat_w          : POSITIVE := 32; 
+    g_buf_addr_w         : POSITIVE := 7;                         -- Waveform buffer size 2**g_buf_addr_w nof samples
+    g_file_index_arr     : t_nat_natural_arr := array_init(0, 128, 1);  -- default use the instance index as file index 0, 1, 2, 3, 4 ...
+    g_file_name_prefix   : STRING   := "../../data/bf_in_data";   -- Relative path to the hex files that contain the initial data for the memories 
+                                                                  -- The sequence number and ".hex" are added within the entity.
+    g_diag_block_gen_rst : t_diag_block_gen := c_diag_block_gen_rst
+  );
+  PORT (
+    -- System
+    mm_rst           : IN  STD_LOGIC;                                      -- reset synchronous with mm_clk
+    mm_clk           : IN  STD_LOGIC;                                      -- memory-mapped bus clock
+    dp_rst           : IN  STD_LOGIC;                                      -- reset synchronous with st_clk
+    dp_clk           : IN  STD_LOGIC;                                      -- streaming clock domain clock
+    en_sync          : IN  STD_LOGIC := '1';                               -- block generator enable sync pulse in ST dp_clk domain
+    -- MM interface
+    reg_bg_ctrl_mosi : IN  t_mem_mosi := c_mem_mosi_rst;                   -- Memory interface for In System updating of the waveform generator data
+    reg_bg_ctrl_miso : OUT t_mem_miso;                                     -- Memory interface for In System updating of the waveform generator data                                         
+    ram_bg_data_mosi : IN  t_mem_mosi := c_mem_mosi_rst;                   -- Memory interface for In System updating of the waveform generator data
+    ram_bg_data_miso : OUT t_mem_miso;                                     -- Memory interface for In System updating of the waveform generator data                                         
+    -- ST interface
+    out_siso_arr     : IN  t_dp_siso_arr(g_nof_output_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);  -- Default no XON flow control
+    out_sosi_arr     : OUT t_dp_sosi_arr(g_nof_output_streams-1 DOWNTO 0)  -- Output SOSI that contains the waveform data
+  );
+END mms_diag_block_gen;
+
+ARCHITECTURE rtl OF mms_diag_block_gen IS
+
+  CONSTANT c_buf              : t_c_mem  := (latency  => 1,
+                                             adr_w    => g_buf_addr_w,
+                                             dat_w    => g_buf_dat_w,
+                                             nof_dat  => 2**g_buf_addr_w,
+                                             init_sl  => '0');   
+                                             
+  CONSTANT c_post_buf_file    : STRING := ".hex";
+
+  TYPE t_buf_dat_arr IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(g_buf_dat_w -1 DOWNTO 0);
+  TYPE t_buf_adr_arr IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(g_buf_addr_w-1 DOWNTO 0);
+
+  SIGNAL st_addr_arr          : t_buf_adr_arr(g_nof_output_streams    -1 DOWNTO 0);
+  SIGNAL st_rd                : STD_LOGIC_VECTOR(g_nof_output_streams -1 DOWNTO 0);
+  SIGNAL st_rdval             : STD_LOGIC_VECTOR(g_nof_output_streams -1 DOWNTO 0);
+  SIGNAL st_rddata_arr        : t_buf_dat_arr(g_nof_output_streams    -1 DOWNTO 0);
+  SIGNAL ram_bg_data_mosi_arr : t_mem_mosi_arr(g_nof_output_streams   -1 DOWNTO 0);
+  SIGNAL ram_bg_data_miso_arr : t_mem_miso_arr(g_nof_output_streams   -1 DOWNTO 0); 
+  SIGNAL bg_ctrl              : t_diag_block_gen;
+  
+BEGIN
+  
+  u_bg_ctrl : ENTITY work.diag_block_gen_reg 
+  GENERIC MAP(
+    g_cross_clock_domain => TRUE,   -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+    g_diag_block_gen_rst => g_diag_block_gen_rst
+  )
+  PORT MAP (
+    mm_rst  => mm_rst,                   -- Clocks and reset
+    mm_clk  => mm_clk,
+    dp_rst  => dp_rst,
+    dp_clk  => dp_clk,
+    mm_mosi => reg_bg_ctrl_mosi,
+    mm_miso => reg_bg_ctrl_miso,
+    bg_ctrl => bg_ctrl                       
+  ); 
+  
+  -- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
+  u_mem_mux_bg_data : ENTITY common_lib.common_mem_mux
+  GENERIC MAP (    
+    g_nof_mosi    => g_nof_output_streams,
+    g_mult_addr_w => g_buf_addr_w
+  )
+  PORT MAP (
+    mosi     => ram_bg_data_mosi,
+    miso     => ram_bg_data_miso,
+    mosi_arr => ram_bg_data_mosi_arr,
+    miso_arr => ram_bg_data_miso_arr
+  );
+  
+  gen_wg_streams : FOR I IN 0 TO g_nof_output_streams-1 GENERATE
+    u_buffer_ram : ENTITY common_lib.common_ram_crw_crw
+      GENERIC MAP (
+        g_ram        => c_buf,
+        -- Sequence number and ".hex" extensie are added to the relative path in case a ram file is provided. 
+        g_init_file  => sel_a_b(g_file_name_prefix = "UNUSED", g_file_name_prefix, g_file_name_prefix & "_" & NATURAL'IMAGE(g_file_index_arr(I)) & c_post_buf_file)    
+      )
+      PORT MAP (
+        -- MM side
+        rst_a     => mm_rst,
+        clk_a     => mm_clk,
+        wr_en_a   => ram_bg_data_mosi_arr(I).wr,
+        wr_dat_a  => ram_bg_data_mosi_arr(I).wrdata(c_buf.dat_w -1 DOWNTO 0),
+        adr_a     => ram_bg_data_mosi_arr(I).address(c_buf.adr_w-1 DOWNTO 0),
+        rd_en_a   => ram_bg_data_mosi_arr(I).rd,
+        rd_dat_a  => ram_bg_data_miso_arr(I).rddata(c_buf.dat_w -1 DOWNTO 0),
+        rd_val_a  => ram_bg_data_miso_arr(I).rdval,
+        -- Waveform side
+        rst_b     => dp_rst,
+        clk_b     => dp_clk,
+        wr_en_b   => '0',
+        wr_dat_b  => (OTHERS =>'0'),
+        adr_b     => st_addr_arr(I), 
+        rd_en_b   => st_rd(I),
+        rd_dat_b  => st_rddata_arr(I),
+        rd_val_b  => st_rdval(I) 
+      );   
+    
+    u_waveform_generator : ENTITY work.diag_block_gen
+      GENERIC MAP (
+        g_blk_sync   => g_blk_sync,
+        g_buf_dat_w  => g_buf_dat_w, 
+        g_buf_addr_w => g_buf_addr_w
+      )
+      PORT MAP (
+        rst        => dp_rst, 
+        clk        => dp_clk, 
+        buf_addr   => st_addr_arr(I),       
+        buf_rden   => st_rd(I),          
+        buf_rddat  => st_rddata_arr(I),       
+        buf_rdval  => st_rdval(I),          
+        ctrl       => bg_ctrl,
+        en_sync    => en_sync,
+        out_siso   => out_siso_arr(I),
+        out_sosi   => out_sosi_arr(I)
+      ); 
+  END GENERATE;
+  
+END rtl;

libraries/base/diag/tb/vhdl/tb_diag_regression.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Regression multi TB for DIAG library
+-- Description:
+--   All TB are self checking. If some component TB fails then simulate that TB
+--   seperately to find the cause.
+-- Usage:
+-- > as 3
+-- > run -all
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY tb_diag_regression IS
+END tb_diag_regression;
+
+
+ARCHITECTURE tb OF tb_diag_regression IS
+BEGIN
+
+  u_tb_diag_block_gen             : ENTITY work.tb_diag_block_gen;
+  u_tb_mms_diag_block_gen         : ENTITY work.tb_mms_diag_block_gen;
+  
+END tb;