Item 100 o) is also fixed by hdl_lib_excludes key.

tools/hdltool_readme.txt

@@ -770,26 +770,22 @@ n) Rename keys:
    * Rename modelsim_compile_ip_files into more precise name eg. modelsim_execute or modelsim_pre_execute.
    * Rename key test_bench_files into sim_files, but does the hdllib.cfg become more clear to do this rename?
    
-o) How to avoid Quartus exit due to IP that is included at configuration, but not used at synthesis
-   * due to test_bench_files (FIXED - erko)
+o) (FIXED - erko) How to avoid Quartus exit due to IP that is included at configuration, but not used at synthesis
+   * (FIXED - erko) due to test_bench_files --> 'hdl_lib_uses_sim' key
    Quartus can exit with error if IP is included in the hdl_lib_uses list of libraries but not actually used in
    the design, eg due to a sdc file that is then sourced but that cannot find some IP signals. Having a seperate
    hdl_lib_uses_synth and hdl_lib_uses_sim key solves this issue, by avoiding that libraries that are only needed
    for test bench simulation get included in the list for synthesis.
-   
-   * due to not-generate a certain IO component at compile time
-   If the error is changed into warning then Quartus continues. Such modification of the sdc file could be automated
-   by using 'sed' to edit the sdc after it was generated by generate_ip.tcl.
+   * (FIXED - erko) due to not-generate a certain IO component at compile time --> 'hld_lib_excludes' key
    In some designs we want to be able to temporarily disable the synthesis of an IO component (eg. io_ddr) to reduce
-   synthesis time. In that case the Quartus should not need to source the qip and sdc settings for that IP. It 
-   would be sufficient to only source an io_ddr entity with empty architecture. We already have the revision capability
-   for designs and this could also be applied to IO libraries. Still the question remains how select between using
-   the component declaration only library when it is not used for synthesis and how to include the full library when
-   it is used for synthesis. This could be done if the io_ddr library is only included at the design level, because
-   then the design that uses the io_ddr has hdl_lib_uses_synth = io_ddr in its hdllib.cfg whereas the design that does not
-   use io_ddr should in have hdl_lib_uses_synth = io_ddr_empty, where io_ddr_empty is a revision of io_ddr with only the
-   entity and an emtpy architecture. Erko: the best scheme is probably to use the hld_lib.excludes key to
-   exclude the DDR IP library in the hdllib.cfg of the design revision that has the io_ddr but does not generate it.
+   synthesis time. In that case the Quartus should not need to source the qip and sdc settings for that IP. The 
+   IP can be excluded for a design by using the 'hld_lib_excludes' key to exclude the DDR IP library in the hdllib.cfg
+   of the design revision that has the io_ddr but does not generate it. The exclusion cannot be done at the io_ddr
+   or tech_ddr level, because these are instantiated as entities. Therefore the eclusiong is done at the IP level 
+   because the IP is instantiated as component. Hence the exclusion works because for a component instance that is 
+   not used only the component declaration (in the component package) needs to be known by the tools. Hence the 
+   exclusion makes use of the same VHDL component mechanism as the technology independence.
+