Removed ctlr_init_done. Now report ctlr_init_done via dvr_done.

libraries/io/ddr/src/vhdl/io_ddr.vhd

@@ -127,7 +127,6 @@ ENTITY io_ddr IS
     ctlr_clk_in        : IN    STD_LOGIC;  -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
     ctlr_rst_in        : IN    STD_LOGIC;  -- connect ctlr_rst_out to ctlr_rst_in at top level
     
-    ctlr_init_done     : OUT   STD_LOGIC;
     ctlr_rdy           : OUT   STD_LOGIC;
 
     -- Driver clock domain
@@ -184,7 +183,7 @@ ARCHITECTURE str OF io_ddr IS
   SIGNAL ctlr_dvr_end_addr     : t_tech_ddr_addr;
   SIGNAL ctlr_dvr_wr_flush_en  : STD_LOGIC := '0';
     
-  SIGNAL i_ctlr_init_done      : STD_LOGIC;
+  SIGNAL ctlr_init_done        : STD_LOGIC;
 
   SIGNAL ctlr_mosi             : t_tech_ddr_mosi := c_tech_ddr_mosi_rst;
   SIGNAL ctlr_miso             : t_tech_ddr_miso := c_tech_ddr_miso_rst;
@@ -208,7 +207,6 @@ ARCHITECTURE str OF io_ddr IS
   
 BEGIN 
 
-  ctlr_init_done <= i_ctlr_init_done;
   ctlr_rdy <= ctlr_miso.waitrequest_n;
   
   u_io_ddr_cross_domain : ENTITY work.io_ddr_cross_domain
@@ -374,7 +372,7 @@ BEGIN
     rd_src_out      => ctlr_rd_src_out,
     rd_src_in       => ctlr_rd_src_in,
 
-    ctlr_init_done  => i_ctlr_init_done,
+    ctlr_init_done  => ctlr_init_done,
     ctlr_miso       => ctlr_miso,
     ctlr_mosi       => ctlr_mosi
   );
@@ -395,7 +393,7 @@ BEGIN
     ctlr_gen_clk_2x   => OPEN,
     ctlr_gen_rst_2x   => OPEN,
 
-    ctlr_init_done    => i_ctlr_init_done,
+    ctlr_init_done    => ctlr_init_done,
 
     ctlr_mosi         => ctlr_mosi,
     ctlr_miso         => ctlr_miso,

libraries/io/ddr/src/vhdl/io_ddr_driver.vhd

@@ -265,6 +265,7 @@ BEGIN
         nxt_state <= s_wait2;
 
       WHEN s_idle =>
+        nxt_dvr_done <= '1';
         IF dvr_en = '1' THEN  
           nxt_cur_address <= start_address; 
           nxt_dvr_done    <= '0';
@@ -273,7 +274,7 @@ BEGIN
      
       WHEN OTHERS => -- s_init
         IF ctlr_init_done = '1' THEN
-          nxt_state <= s_idle;
+          nxt_state <= s_idle;  -- and assert dvr_done when in s_idle
         END IF;
       
     END CASE;

libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd

@@ -98,7 +98,6 @@ ARCHITECTURE str of tb_io_ddr IS
   SIGNAL dp_rst               : STD_LOGIC;
 
   SIGNAL ctlr_rdy             : STD_LOGIC;
-  SIGNAL ctlr_init_done       : STD_LOGIC;
 
   SIGNAL dvr_start_addr       : t_tech_ddr_addr; 
   SIGNAL dvr_end_addr         : t_tech_ddr_addr;
@@ -154,14 +153,13 @@ BEGIN
     snk_diag_en     <= '0';
     expected_cnt    <= 0;
 
-    proc_common_wait_until_high(ctlr_clk, ctlr_init_done);
-    proc_common_wait_some_cycles(ctlr_clk, 2);  -- Give the driver FSM a cycle to go into idle mode
+    proc_common_wait_until_high(dvr_clk, dvr_done);
     
     -- Start diagnostics source for write and sink for verify read
     src_diag_en <= '1';
     snk_diag_en <= '1';
     
-    -- After reset even when dvr_wr_flush_en='0' then the write FIFO is flushed until the first write access is started
+    -- After reset the write FIFO is flushed until the first write access is started, even when dvr_wr_flush_en='0'
     proc_common_wait_some_cycles(ctlr_clk, 100);
     
     FOR R IN 0 TO g_nof_repeat-1 LOOP
@@ -288,7 +286,6 @@ BEGIN
     ctlr_clk_in        => ctlr_clk,  -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
     ctlr_rst_in        => ctlr_rst,
     
-    ctlr_init_done     => ctlr_init_done,
     ctlr_rdy           => ctlr_rdy,
 
     -- Driver clock domain