Better indentation

libraries/technology/mult/tech_mult.vhd

@@ -54,7 +54,7 @@ ENTITY tech_mult IS
   );
 END tech_mult;
 
-ARCHITECTURE str of tech_mult is 
+ARCHITECTURE str of tech_mult is
 
   -- When g_out_p_w < g_in_a_w+g_in_b_w then the LPM_MULT truncates the LSbits of the product. Therefore
   -- define c_prod_w to be able to let common_mult truncate the LSBits of the product.
@@ -66,87 +66,87 @@ begin
 
   gen_ip_stratixiv_ip : IF (g_technology=c_tech_stratixiv AND g_variant="IP") GENERATE
     u0 : ip_stratixiv_mult
-  GENERIC MAP(
-    g_in_a_w           => g_in_a_w,
-    g_in_b_w           => g_in_b_w,
-    g_out_p_w          => g_out_p_w,
-    g_nof_mult         => g_nof_mult,
-    g_pipeline_input   => g_pipeline_input,
-    g_pipeline_product => g_pipeline_product,
-    g_pipeline_output  => g_pipeline_output,
-    g_representation   => g_representation
-  )
-  PORT MAP(
-    clk        => clk,
-    clken      => clken,
-    in_a       => in_a,
-    in_b       => in_b,
-    out_p      => prod
+    GENERIC MAP(
+      g_in_a_w           => g_in_a_w,
+      g_in_b_w           => g_in_b_w,
+      g_out_p_w          => g_out_p_w,
+      g_nof_mult         => g_nof_mult,
+      g_pipeline_input   => g_pipeline_input,
+      g_pipeline_product => g_pipeline_product,
+      g_pipeline_output  => g_pipeline_output,
+      g_representation   => g_representation
+    )
+    PORT MAP(
+      clk        => clk,
+      clken      => clken,
+      in_a       => in_a,
+      in_b       => in_b,
+      out_p      => prod
     );
   END GENERATE;
-   
+
   gen_ip_stratixiv_rtl : IF (g_technology=c_tech_stratixiv AND g_variant="RTL") GENERATE
     u0 : ip_stratixiv_mult_rtl
-  GENERIC MAP(
-    g_in_a_w           => g_in_a_w,
-    g_in_b_w           => g_in_b_w,
-    g_out_p_w          => g_out_p_w,
-    g_nof_mult         => g_nof_mult,
-    g_pipeline_input   => g_pipeline_input,
-    g_pipeline_product => g_pipeline_product,
-    g_pipeline_output  => g_pipeline_output,
-    g_representation   => g_representation
-  )
-  PORT MAP(
-    rst        => rst,
-    clk        => clk,
-    clken      => clken,
-    in_a       => in_a,
-    in_b       => in_b,
-    out_p      => prod
+    GENERIC MAP(
+      g_in_a_w           => g_in_a_w,
+      g_in_b_w           => g_in_b_w,
+      g_out_p_w          => g_out_p_w,
+      g_nof_mult         => g_nof_mult,
+      g_pipeline_input   => g_pipeline_input,
+      g_pipeline_product => g_pipeline_product,
+      g_pipeline_output  => g_pipeline_output,
+      g_representation   => g_representation
+    )
+    PORT MAP(
+      rst        => rst,
+      clk        => clk,
+      clken      => clken,
+      in_a       => in_a,
+      in_b       => in_b,
+      out_p      => prod
     );
   END GENERATE;
 
   gen_ip_arria10_ip : IF (g_technology=c_tech_arria10 AND g_variant="IP") GENERATE
     u0 : ip_arria10_mult
-  GENERIC MAP(
-    g_in_a_w           => g_in_a_w,
-    g_in_b_w           => g_in_b_w,
-    g_out_p_w          => g_out_p_w,
-    g_nof_mult         => g_nof_mult,
-    g_pipeline_input   => g_pipeline_input,
-    g_pipeline_product => g_pipeline_product,
-    g_pipeline_output  => g_pipeline_output,
-    g_representation   => g_representation
-  )
-  PORT MAP(
-    clk        => clk,
-    clken      => clken,
-    in_a       => in_a,
-    in_b       => in_b,
-    out_p      => prod
+    GENERIC MAP(
+      g_in_a_w           => g_in_a_w,
+      g_in_b_w           => g_in_b_w,
+      g_out_p_w          => g_out_p_w,
+      g_nof_mult         => g_nof_mult,
+      g_pipeline_input   => g_pipeline_input,
+      g_pipeline_product => g_pipeline_product,
+      g_pipeline_output  => g_pipeline_output,
+      g_representation   => g_representation
+    )
+    PORT MAP(
+      clk        => clk,
+      clken      => clken,
+      in_a       => in_a,
+      in_b       => in_b,
+      out_p      => prod
     );
   END GENERATE;
-   
+
   gen_ip_arria10_rtl : IF (g_technology=c_tech_arria10 AND g_variant="RTL") GENERATE
     u0 : ip_arria10_mult_rtl
-  GENERIC MAP(
-    g_in_a_w           => g_in_a_w,
-    g_in_b_w           => g_in_b_w,
-    g_out_p_w          => g_out_p_w,
-    g_nof_mult         => g_nof_mult,
-    g_pipeline_input   => g_pipeline_input,
-    g_pipeline_product => g_pipeline_product,
-    g_pipeline_output  => g_pipeline_output,
-    g_representation   => g_representation
-  )
-  PORT MAP(
-    rst        => rst,
-    clk        => clk,
-    clken      => clken,
-    in_a       => in_a,
-    in_b       => in_b,
-    out_p      => prod
+    GENERIC MAP(
+      g_in_a_w           => g_in_a_w,
+      g_in_b_w           => g_in_b_w,
+      g_out_p_w          => g_out_p_w,
+      g_nof_mult         => g_nof_mult,
+      g_pipeline_input   => g_pipeline_input,
+      g_pipeline_product => g_pipeline_product,
+      g_pipeline_output  => g_pipeline_output,
+      g_representation   => g_representation
+    )
+    PORT MAP(
+      rst        => rst,
+      clk        => clk,
+      clken      => clken,
+      in_a       => in_a,
+      in_b       => in_b,
+      out_p      => prod
     );
   END GENERATE;