added zipped sof files for unb2c

boards/uniboard2c/designs/refdesigns/ddr4/doc/README_ddr4.txt

+Tue Jul 21 18:00:02 CEST 2015
+
+Instructions of how to set the fields in the IP catalog for ddr4.qsys
+
+(see the datasheets in the subdir datasheet/micron/* )
+
+All settings are based on the Micron DDR4 module: MTA18ASF1G72HZ-2G1A1ZJ
+This is a 8GB SODIMM dual rank 
+-2G1 stands for: PC4-2133 with CAS latency CL=15
+
+pagesize is 1KB (page 2)
+
+The IC's on the module: MT40A512M8 (4Gb)
+The IC marking is (photo): D9RGQ but should be -093E 
+
+
+Quartus IP catalog "Arria10 External Memory Interface" fill in:
+(the page numbers are of the MT40A512M8 datasheet)
+
+
+1. Preset selection from library: DDR4-2133P CL15 1CS 4Gb (512Mb x 8)
+   This means a single rank DDR4
+   The ES of Arria10 does not support dual rank (see Errata document)
+   After setting the ddr4.qsys IP the CS1, CKE1 and ODT1 lines to the module should be manually disabled,
+   then the module acts as a single rank
+
+2. Tab "General"
+   For the Memory clock frequency select 800.0 MHz or 700 MHz instead of 1066.667 MHz because the ES of Arria does not 
+   support higher Memory frequencies.
+   Set the PLL reference clock frequency to 200 MHz
+   PLL reference clock jitter=10.0 ps
+
+
+3. Tab "I/O"
+   Address/Command:
+     I/O standard=SSTL-12
+     Output mode: 40 ohm without calibration
+     Slew rate=fast
+
+   Memory clock:
+     I/O standard=SSTL-12
+     Output mode: 40 ohm without calibration
+     Slew rate=fast
+
+   Data bus
+     I/O standard=1.2V POD
+     Output mode: 34 ohm with calibration
+     Input mode: 60 ohm with calibration
+     Starting Vrefin=60.0
+
+   RZQ=240 ohm
+
+4. Tab "Memory Topology"
+   Memory format=SODIMM
+   DQ width=72
+
+   unselect: Data mask
+   unselect: Enable ALERT
+
+   In the section "Mode Register Settings"
+   CAS latency: See page 312 table 138 (column 15-15-15)
+   for 700MHz set it to 12 (mode register 0)
+   Memory write CAS latency also to 9 (mode register 2)
+
+   Output drive strength setting=RZQ/7 (mode register 1)
+   ODT Rtt nominal value=RZQ/5 (mode register 1)
+
+   Dynamic ODT (Rtt_WR)= OFF (mode register 2)
+
+   ODT Activation Settings to Default
+
+
+5. Tab "Memory Timing"
+   Speed bin=-2133 
+
+   (timings are recalculated for 800MHz Memory clock)
+
+   tIS (base) = 80 ps          (table 143, page 321)
+   tIS (base) AC level = 100mV (table 80, page 254)
+   tIH (base) = 105 ps         (table 143, page 321)
+   tIH (base) DC level = 75mV  (table 800, page 254)
+   tdIVW_dj = 0.1 UI   (table 82, page 257) Max=0.2UI but 0.1UI is default
+   VdiVW_total = 136mV (table 82, page 257)
+ * tDQSQ = 114ps (page 319) (0.16*UId. UI=tCK/2.  tCK=1/700e6)
+ * tQH = 0.38    (page 319) (0.76*UId)/tCK 
+   tDQSCK = 170  (page 320) (within -180 and 180)
+   tDQSS = 0.27  (page 320)
+   tQSH = 0.38   (page 320)
+   tDSH = 0.18   (page 320)
+   tDSS = 0.18   (page 320)
+ * tWLS = 185.7  (page 328) 0.13*CK (CK=1/700e6)
+ * tWLH = 185.7  (page 328) 0.13*CK (CK=1/700e6)
+   tINIT = 500us (page 29)
+   tMRD = 8      (page 323)
+   tRAS = 33     (page 312)
+   tRCD = 14.06  (page 312)
+   tRP  = 14.06  (page 312)
+   tWR  = 15     (page 322)
+
+ * tRRD_S = 3     (page 176,321) should be 3.7ns. Using 3*CK=3.75ns (CK=1/700e6)
+ * tRRD_L = 4     (page 176,321) should be 5.3ns. Using 4*CK=5ns
+ * tFAW   = 21 ns (page 322)
+   tCCD_S = 4     (page 176,321)
+ * tCCD_L = 4     (page 176,321) should be 5.355ns. Using 4*CK=5ns
+ * tWTR_S = 2     (page 177,321) should be 2.5ns. Using 2*CK=2.5ns
+ * tWTR_L = 6     (page 177,321) should be 7.5ns. Using 6*CK=7.5ns
+
+   tRFC = 260 ns  (see page 325) 
+   tREFI = 7.8 us (see page 325)
+
+   (* marked lines have to be recalculated when using different Memory clock frequency)
+
+6. Tab "Board Timing"
+   Slew Rates (numbers from simulation):
+     CK              2.43
+     A4              1.16
+     DQS0 FPGA->DIMM 3.7
+     DQ0  FPGA->DIMM 2.16
+     DQS0 DIMM->FPGA 3.7
+     DQ0  DIMM->FPGA 2.2
+
+   Crosstalk: use default values
+
+   Board/Package skews
+     2x radiobuttons "Package deskewed..."        = OFF
+     Maximum board skew within DQS group          = 0.03 ns
+     Maximum board skew within addr/command group = 0.146 ns
+   
+     Avg delay difference between DQS and CK      = -0.21 ns
+     Max delay difference between DIMMs           = 0.0 ns
+     Max skew between DQS groups                  = 0.133 ns
+     Avg delay difference between addr/cmd and CK = 0.013 ns
+
+     Max CK delay to DIMM  = 0.252 ns
+     Max DQS delay to DIMM = 0.323 ns
+
+10. compile steps
+
+  click save ddr4.qsys
+  click "generate HDL"
+  click "generate Example Design"
+  close IP catalog GUI
+
+  run:
+  cd emif_0_example_design
+  . ${RADIOHDL_GEAR}/quartus/set_quartus unb2 && quartus_sh -t make_qii_design.tcl
+
+  add to qii/ed_synth.qsf:
+  source ../../unb2_pins_ed_synth.tcl
+
+  edit qii/synth/ed_synth.v:
+  add to module ed_synth the wires:
+
+    output  wire [8:0]  emif_0_example_design_mem_mem_dbi_n,
+    output wire cs1_export,
+    output wire cke1_export,
+    output wire odt1_export,
+    input  wire testio1
+
+  add below local wires:
+
+    assign cs1_export = testio1;
+    assign cke1_export = ~testio1;
+    assign odt1_export = ~testio1;
+    assign emif_0_example_design_mem_mem_dbi_n[0] = ~testio1;
+    assign emif_0_example_design_mem_mem_dbi_n[1] = ~testio1;
+    assign emif_0_example_design_mem_mem_dbi_n[2] = ~testio1;
+    assign emif_0_example_design_mem_mem_dbi_n[3] = ~testio1;
+    assign emif_0_example_design_mem_mem_dbi_n[4] = ~testio1;
+    assign emif_0_example_design_mem_mem_dbi_n[5] = ~testio1;
+    assign emif_0_example_design_mem_mem_dbi_n[6] = ~testio1;
+    assign emif_0_example_design_mem_mem_dbi_n[7] = ~testio1;
+    assign emif_0_example_design_mem_mem_dbi_n[8] = ~testio1;
+
+  (assuming testio1 is pulled up to VCC)
+
+
+
+
+

boards/uniboard2c/designs/unb2c_led/hdllib.cfg

+hdl_lib_name = unb2c_led
+hdl_library_clause_name = unb2c_led_lib
+hdl_lib_uses_synth = common technology unb2c_board
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    src/vhdl/unb2c_led.vhd
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+
+quartus_qsf_files =
+    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+
+quartus_sdc_files =
+    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+
+quartus_tcl_files =
+    quartus/unb2c_minimal_pins.tcl
+
+quartus_vhdl_files = 
+
+quartus_qip_files =
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+

boards/uniboard2c/designs/unb2c_led/quartus/unb2c_minimal_pins.tcl

+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl

boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2016
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2c_board_lib.unb2c_board_pkg.ALL;
+
+ENTITY unb2c_led IS
+  GENERIC (
+    g_design_name   : STRING  := "unb2c_led";
+    g_design_note   : STRING  := "UNUSED";
+    g_technology    : NATURAL := c_tech_arria10_e2sg;
+    g_sim           : BOOLEAN := FALSE; --Overridden by TB
+    g_sim_unb_nr    : NATURAL := 0;
+    g_sim_node_nr   : NATURAL := 0;
+    g_stamp_date    : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
+    g_stamp_time    : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
+    g_stamp_svn     : NATURAL := 0;  -- SVN revision    -- set by QSF
+    g_factory_image : BOOLEAN := TRUE
+  );
+  PORT (
+    CLK          : IN    STD_LOGIC;
+    ETH_CLK      : IN    STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+    TESTIO       : INOUT STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
+    QSFP_LED     : OUT   STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+  );
+END unb2c_led;
+
+
+ARCHITECTURE str OF unb2c_led IS
+
+  -- Firmware version x.y
+  CONSTANT c_fw_version         : t_unb2c_board_fw_version := (2, 0);
+  CONSTANT c_reset_len          : NATURAL := 40000; --4;  -- >= c_meta_delay_len from common_pkg
+  CONSTANT c_mm_clk_freq        : NATURAL := c_unb2c_board_mm_clk_freq_50M;
+
+  -- System
+  SIGNAL divclk                 : STD_LOGIC;
+  SIGNAL mm_locked              : STD_LOGIC;
+
+  SIGNAL clk125                 : STD_LOGIC := '1';
+  SIGNAL clk100                 : STD_LOGIC := '1';
+  SIGNAL clk50                  : STD_LOGIC := '1';
+
+  SIGNAL cs_sim                 : STD_LOGIC;
+  SIGNAL xo_ethclk              : STD_LOGIC;
+  SIGNAL xo_rst                 : STD_LOGIC;
+  SIGNAL xo_rst_n               : STD_LOGIC;
+  SIGNAL mm_rst                 : STD_LOGIC;
+
+  SIGNAL pulse_10Hz             : STD_LOGIC;
+  SIGNAL pulse_10Hz_extended    : STD_LOGIC;
+  SIGNAL mm_pulse_ms            : STD_LOGIC;
+  SIGNAL mm_pulse_s             : STD_LOGIC;
+  
+  SIGNAL led_toggle             : STD_LOGIC;
+  SIGNAL led_flash              : STD_LOGIC;
+  SIGNAL led_flash_red          : STD_LOGIC;
+  SIGNAL led_flash_green        : STD_LOGIC;
+
+  -- QSFP leds
+  SIGNAL qsfp_green_led_arr     : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+  SIGNAL qsfp_red_led_arr       : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+
+  constant c_CNT_1HZ : natural := 20000000;
+  signal r_CNT_1HZ : natural range 0 to c_CNT_1HZ;
+  signal r_TOGGLE_1HZ   : std_logic := '0';
+  signal leddiv   : std_logic := '0';
+  signal clk200 : std_logic;
+
+BEGIN
+  xo_rst_n   <= NOT xo_rst;
+
+  -----------------------------------------------------------------------------
+  -- xo_ethclk = ETH_CLK
+  -----------------------------------------------------------------------------
+
+  divclk <= clk200; --ETH_CLK(1);   -- use the ETH_CLK pin as xo_clk
+
+  leddiv <= r_TOGGLE_1HZ;
+
+  p_led : process (divclk) is
+  begin
+    if rising_edge(divclk) then
+      if r_CNT_1HZ = c_CNT_1HZ-1 then  -- -1, since counter starts at 0
+        r_TOGGLE_1HZ <= not r_TOGGLE_1HZ;
+        r_CNT_1HZ    <= 0;
+      else
+        r_CNT_1HZ <= r_CNT_1HZ + 1;
+      end if;
+    end if;
+  end process p_led;
+
+
+  -- by using the fpll, the CLKUSR is used for calibration. So in case fpll does not work, check CLKUSR
+
+  u_unb2c_board_clk200_pll : ENTITY unb2c_board_lib.unb2c_board_clk200_pll
+  GENERIC MAP (
+    g_use_fpll   => TRUE, --FALSE, -- switch fpll or fixedpll
+    g_technology => g_technology
+  )
+  PORT MAP (
+    arst       => xo_rst,
+    clk200     => CLK,
+    st_clk200  => clk200
+  );
+
+
+
+  xo_ethclk <= ETH_CLK(0);   -- use the ETH_CLK pin as xo_clk
+
+  u_common_areset_xo : ENTITY common_lib.common_areset
+  GENERIC MAP (
+    g_rst_level => '1',       -- power up default will be inferred in FPGA
+    g_delay_len => c_reset_len
+  )
+  PORT MAP (
+    in_rst    => '0',         -- release reset after some clock cycles
+    clk       => xo_ethclk,
+    out_rst   => xo_rst
+  );
+
+
+
+  u_unb2c_board_clk125_pll : ENTITY unb2c_board_lib.unb2c_board_clk125_pll
+  GENERIC MAP (
+    g_use_fpll   => TRUE, --FALSE, -- switch fpll or fixedpll
+    g_technology => g_technology
+  )
+  PORT MAP (
+    arst       => xo_rst,
+    clk125     => xo_ethclk,
+    c1_clk50   => clk50,
+    pll_locked => mm_locked
+  );
+
+  u_unb2c_board_node_ctrl : ENTITY unb2c_board_lib.unb2c_board_node_ctrl
+  GENERIC MAP (
+    g_pulse_us => c_mm_clk_freq / (10**6)     -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+  )
+  PORT MAP (
+    -- MM clock domain reset
+    mm_clk      => clk50,
+    mm_locked   => mm_locked,
+    mm_rst      => mm_rst,
+    -- WDI extend
+    mm_wdi_in   => mm_pulse_s,
+    -- Pulses
+    mm_pulse_us => OPEN,
+    mm_pulse_ms => mm_pulse_ms,
+    mm_pulse_s  => mm_pulse_s  -- could be used to toggle a LED
+  );
+
+  ------------------------------------------------------------------------------
+  -- Toggle red LED when unb2c_minimal is running, green LED for other designs.
+  ------------------------------------------------------------------------------
+  led_flash_red   <= sel_a_b(g_factory_image=TRUE,  led_flash, '0');
+  led_flash_green <= sel_a_b(g_factory_image=FALSE, led_flash, '0');
+
+
+  u_extend : ENTITY common_lib.common_pulse_extend
+  GENERIC MAP (
+    g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
+  )
+  PORT MAP (
+    rst     => mm_rst,
+    clk     => clk50,
+    p_in    => mm_pulse_s,
+    ep_out  => led_flash
+  );
+
+
+
+
+  -- Red LED control
+  TESTIO(c_unb2c_board_testio_led_red)   <= led_flash_red;
+
+  -- Green LED control
+  TESTIO(c_unb2c_board_testio_led_green) <= led_flash_green;
+
+
+  
+  u_common_pulser_10Hz : ENTITY common_lib.common_pulser
+  GENERIC MAP (
+    g_pulse_period => 100,
+    g_pulse_phase  => 100-1
+  )
+  PORT MAP (
+    rst            => mm_rst,
+    clk            => clk50,
+    clken          => '1',
+    pulse_en       => mm_pulse_ms,
+    pulse_out      => pulse_10Hz
+  );
+
+  u_extend_10Hz : ENTITY common_lib.common_pulse_extend
+  GENERIC MAP (
+    g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
+  )
+  PORT MAP (
+    rst     => mm_rst,
+    clk     => clk50,
+    p_in    => pulse_10Hz,
+    ep_out  => pulse_10Hz_extended
+  );
+
+  u_toggle : ENTITY common_lib.common_toggle
+  PORT MAP (
+    rst         => mm_rst,
+    clk         => clk50,
+    in_dat      => mm_pulse_s,
+    out_dat     => led_toggle
+  );
+
+  QSFP_LED(2)  <= pulse_10Hz_extended;
+
+  QSFP_LED(6)  <= led_toggle;
+  QSFP_LED(7)  <= NOT led_toggle;
+  QSFP_LED(10) <= leddiv;
+  QSFP_LED(11) <= NOT leddiv;
+
+  -- red LEDs on bottom
+  QSFP_LED(1)  <= clk200;
+  QSFP_LED(5)  <= ETH_CLK(0);
+  QSFP_LED(9)  <= ETH_CLK(1);
+
+END str;
+

boards/uniboard2c/designs/unb2c_test/doc/README_test_ddr.txt

+Test env: hiemstra@dop421:~/git/upe_gear/peripherals
+
+util_system_info.py --unb2 0 --pn2 0:3 -n4
+export RADIOHDL=/home/hiemstra/git/hdl
+
+# single node test:
+python3 tc_unb2_test_ddr.py --unb2 0 --pn2 0 -s I,II -n 4294967295 --rep 1
+
+# all nodes test (short duration):
+python3 tc_unb2_test_ddr.py --unb2 0 --pn2 0:3 -s I,II -n 4294967295 --rep 10 > ddr4_24h_stress_test.txt
+
+# 24 hours
+python3 tc_unb2_test_ddr.py --unb2 0 --pn2 0:3 -s I,II -n 4294967295 --rep 13500 > ddr4_24h_stress_test.txt
+
+

boards/uniboard2c/designs/unb2c_test/doc/README_test_sens.txt

+Test env: hiemstra@dop421:~/git/upe_gear/peripherals
+
+util_system_info.py --unb2 0 --pn2 0:3 -n4
+util_unb_fpga_sens.py --unb2 0 --pn2 0:3 -n99
+