Verify g_nof_samples_per_packet = 2, g_nof_blocks_per_sync = 1, g_gapsize = 0, 1.

libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd

@@ -45,6 +45,9 @@ ENTITY tb_diag_block_gen IS
     -- general
     g_flow_control_verify    : t_dp_flow_control_enum := e_active;  -- always active, random or pulse flow control
     -- specific
+    g_nof_samples_per_packet : NATURAL := 2;  -- >= 2
+    g_nof_blocks_per_sync    : NATURAL := 10;  -- >= 1
+    g_gapsize                : NATURAL := 32;  -- >= 0
     g_buf_adr_w      : NATURAL := 7;   -- Waveform buffer address width (requires corresponding c_buf_file)
     g_buf_dat_w      : NATURAL := 32;  -- Waveform buffer stored data width (requires corresponding c_buf_file)
     g_try_phasor     : BOOLEAN := FALSE  -- use TRUE to see BG phasor in wave window with out_sosi.re/im in radix 
@@ -92,17 +95,15 @@ ARCHITECTURE tb OF tb_diag_block_gen IS
   -- Default BG control
   CONSTANT c_bg_ctrl    : t_diag_block_gen := (        '0',      
                                                        '0',      
-                                               TO_UVEC(96, c_diag_bg_samples_per_packet_w), 
-                                               TO_UVEC(10, c_diag_bg_blocks_per_sync_w),      
-                                               TO_UVEC(32, c_diag_bg_gapsize_w), 
+                                               TO_UVEC(g_nof_samples_per_packet, c_diag_bg_samples_per_packet_w),
+                                               TO_UVEC(g_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+                                               TO_UVEC(g_gapsize, c_diag_bg_gapsize_w),
                                                TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),      
                                                TO_UVEC(95, c_diag_bg_mem_high_adrs_w), 
                                                TO_UVEC(42, c_diag_bg_bsn_init_w));
   CONSTANT c_bg_period  : NATURAL := TO_UINT(c_bg_ctrl.samples_per_packet) + TO_UINT(c_bg_ctrl.gapsize);
   
   -- Some alternative BG control settings
-  CONSTANT c_more_samples_per_packet        : NATURAL := c_buf.nof_dat;
-  CONSTANT c_less_samples_per_packet        : NATURAL := 5;
   CONSTANT c_alternative_mem_low_adrs       : NATURAL := 1;
   CONSTANT c_alternative_mem_high_adrs      : NATURAL := 64;
   CONSTANT c_alternative_data_gap           : NATURAL := 1+c_alternative_mem_low_adrs;
@@ -111,7 +112,7 @@ ARCHITECTURE tb OF tb_diag_block_gen IS
   CONSTANT c_bg_ctrl2   : t_diag_block_gen := (        '0',      
                                                        '0',      
                                                TO_UVEC(17, c_diag_bg_samples_per_packet_w), 
-                                               TO_UVEC(10, c_diag_bg_blocks_per_sync_w),      
+                                               TO_UVEC(g_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
                                                TO_UVEC( 0, c_diag_bg_gapsize_w), 
                                                TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),      
                                                TO_UVEC(16, c_diag_bg_mem_high_adrs_w), 
@@ -142,7 +143,7 @@ ARCHITECTURE tb OF tb_diag_block_gen IS
   SIGNAL out_siso       : t_dp_siso;
   SIGNAL out_sosi       : t_dp_sosi;
   SIGNAL prev_out_sosi  : t_dp_sosi;
-  SIGNAL hold_sop       : STD_LOGIC;
+  SIGNAL hold_sop       : STD_LOGIC := '0';
   SIGNAL last_size      : NATURAL;
   SIGNAL exp_size       : NATURAL;
   SIGNAL cnt_size       : NATURAL;

libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd

@@ -45,12 +45,17 @@ BEGIN
   -- -- general
   -- g_flow_control_verify    : t_dp_flow_control_enum := e_active;  -- always active, random or pulse flow control
   -- -- specific
+  -- g_nof_samples_per_packet : NATURAL := 96;
+  -- g_nof_blocks_per_sync    : NATURAL := 10;
+  -- g_gapsize                : NATURAL := 32;  -- >= 0
   -- g_buf_adr_w      : NATURAL := 7;   -- Waveform buffer address width (requires corresponding c_buf_file)
   -- g_buf_dat_w      : NATURAL := 32   -- Waveform buffer stored data width (requires corresponding c_buf_file)
   -- g_try_phasor     : BOOLEAN := FALSE  -- use TRUE to see BG phasor in wave window with out_sosi.re/im in radix 
                                           -- decimal and analogue format, no self test
 
-  u_bg         : ENTITY work.tb_diag_block_gen GENERIC MAP (e_active,  7, 32, FALSE);
-  u_bg_ready   : ENTITY work.tb_diag_block_gen GENERIC MAP (e_random,  7, 32, FALSE);
-  
+  u_bg               : ENTITY work.tb_diag_block_gen GENERIC MAP (e_active, 96, 10, 32, 7, 32, FALSE);
+  u_bg_ready         : ENTITY work.tb_diag_block_gen GENERIC MAP (e_random, 96, 10, 32, 7, 32, FALSE);
+  u_bg_minimal_gap_0 : ENTITY work.tb_diag_block_gen GENERIC MAP (e_active,  2,  1,  0, 7, 32, FALSE);
+  u_bg_minimal_gap_1 : ENTITY work.tb_diag_block_gen GENERIC MAP (e_active,  2,  1,  1, 7, 32, FALSE);
+
 END tb;