Add store_busy.

libraries/base/reorder/src/vhdl/reorder_store.vhd

@@ -47,6 +47,7 @@ use dp_lib.dp_stream_pkg.all;
 --   ch_cnt = nof_ch_in-1.
 -- . The store_done signal occurs when the last data of the input_sosi block
 --   is being written, so 1 cycle after the input_sosi.eop.
+-- . The store_busy goes high at in_sosi.sop and goes low after store_done.
 
 entity reorder_store is
   generic (
@@ -62,6 +63,7 @@ entity reorder_store is
     -- Streaming
     input_sosi    : in  t_dp_sosi;
     -- Timing
+    store_busy    : out std_logic;
     store_done    : out std_logic;
     -- Write databuf control
     store_mosi    : out t_mem_mosi
@@ -80,6 +82,8 @@ architecture rtl of reorder_store is
   signal i_store_mosi     : t_mem_mosi;
   signal nxt_store_mosi   : t_mem_mosi := c_mem_mosi_rst;
 
+  signal store_busy_reg   : std_logic;
+  signal nxt_store_busy   : std_logic;
   signal nxt_store_done   : std_logic;
 begin
   store_mosi <= i_store_mosi;
@@ -91,16 +95,22 @@ begin
       ch_cnt          <= 0;
       -- Output registers.
       i_store_mosi    <= c_mem_mosi_rst;
+      store_busy_reg  <= '0';
       store_done      <= '0';
     elsif rising_edge(clk) then
       -- Internal registers.
       ch_cnt          <= nxt_ch_cnt;
       -- Output registers.
       i_store_mosi    <= nxt_store_mosi;
+      store_busy_reg  <= nxt_store_busy;
       store_done      <= nxt_store_done;
     end if;
   end process;
 
+  store_busy <= nxt_store_busy or store_busy_reg;
+
+  nxt_store_busy <= '0' when ch_cnt = 0 and input_sosi.valid = '0' else '1';
+
   p_ch_cnt : process (ch_cnt, input_sosi, nof_ch_in)
   begin
     nxt_store_done <= '0';