-Fixed hdllib.cfg and mmm_unb1_correlator.vhd.

applications/unb1_correlator/hdllib.cfg

@@ -6,6 +6,8 @@ hdl_lib_technology = ip_stratixiv
 build_dir_sim = $HDL_BUILD_DIR
 build_dir_synth = $HDL_BUILD_DIR
 
+synth_top_level_entity =
+
 quartus_copy_files =
     quartus/qsys_unb1_correlator.qsys .
 

applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd

@@ -107,7 +107,7 @@ ARCHITECTURE str OF mmm_unb1_correlator IS
     -----------------------------------------------------------------------------
     -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
     -----------------------------------------------------------------------------
-    COMPONENT qsys_unb1_test is
+    COMPONENT qsys_unb1_correlator is
         PORT (		  
     
             coe_ram_write_export_from_the_avs_eth_0       : out std_logic;                                        -- export
@@ -298,7 +298,7 @@ ARCHITECTURE str OF mmm_unb1_correlator IS
             ram_diag_bg_clk_export                        : out std_logic;                                        -- export
             ram_diag_bg_reset_export                      : out std_logic                                         -- export
         );
-    end component qsys_unb1_test;
+    end component qsys_unb1_correlator;
 
 BEGIN
 
@@ -344,7 +344,7 @@ BEGIN
   -- SOPC or QSYS for synthesis
   ----------------------------------------------------------------------------
   gen_qsys_unb1_correlator : IF g_sim = FALSE GENERATE
-    u_qsys_unb1_correlator : ENTITY work.qsys_unb1_correlator
+    u_qsys_unb1_correlator : qsys_unb1_correlator
     PORT MAP (
       clk_0                                         => xo_clk, 
       reset_n                                       => xo_rst_n,