Renamed avs_eth into avs2_eth to prepare for using the ETH from RADIOHDL...

Renamed avs_eth into avs2_eth to prepare for using the ETH from RADIOHDL instead of the TSE from UNB in the SOPC for UniBoard1 designs in RADIOHDL.

libraries/io/eth/src/vhdl/avs_eth.vhd → libraries/io/eth/src/vhdl/avs2_eth.vhd

@@ -29,7 +29,7 @@ USE tech_tse_lib.tech_tse_pkg.ALL;
 USE work.eth_pkg.ALL;
 
 
-ENTITY avs_eth IS
+ENTITY avs2_eth IS
   PORT (
     ---------------------------------------------------------------------------
     -- Clock interface
@@ -89,10 +89,10 @@ ENTITY avs_eth IS
     coe_led_crs_export      : OUT STD_LOGIC;
     coe_led_col_export      : OUT STD_LOGIC
   );
-END avs_eth;
+END avs2_eth;
 
 
-ARCHITECTURE wrap OF avs_eth IS
+ARCHITECTURE wrap OF avs2_eth IS
 
   -- Wrap all records to STD_LOGIC
   

libraries/io/eth/src/vhdl/avs_eth_coe.vhd → libraries/io/eth/src/vhdl/avs2_eth_coe.vhd

@@ -23,7 +23,7 @@
 -- Purpose: AVS wrapper to make a MM slave ports for ETH available as conduit
 -- Description:
 -- Remark:
--- . The avs_eth_coe_hw.tcl determines the read latency per port
+-- . The avs2_eth_coe_hw.tcl determines the read latency per port
 
 LIBRARY IEEE, common_lib, tech_tse_lib;
 USE IEEE.std_logic_1164.ALL;
@@ -32,7 +32,7 @@ USE tech_tse_lib.tech_tse_pkg.ALL;
 USE work.eth_pkg.ALL;
 
 
-ENTITY avs_eth_coe IS
+ENTITY avs2_eth_coe IS
   PORT (
     ----------------------------------------------------------------------------
     -- MM side
@@ -98,10 +98,10 @@ ENTITY avs_eth_coe IS
     -- Interrupt Sender interface
     coe_irq_export             : IN  STD_LOGIC
   );
-END avs_eth_coe;
+END avs2_eth_coe;
 
 
-ARCHITECTURE wrap OF avs_eth_coe IS
+ARCHITECTURE wrap OF avs2_eth_coe IS
 BEGIN
 
   ------------------------------------------------------------------------------

libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl

+# TCL File Generated by Component Editor 10.0
+# Wed Apr 20 13:44:54 CEST 2011
+# DO NOT MODIFY
+
+
+# +-----------------------------------
+# | 
+# | avs2_eth_coe "avs2_eth_coe" v1.0
+# | ASTRON 2011.04.20.13:44:54
+# | MM slave port to conduit for the ETH module
+# | 
+# | D:/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/avs2_eth_coe.vhd
+# | 
+# |    ./avs2_eth_coe.vhd syn, sim
+# |    ./D:/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_pkg.vhd syn, sim
+# |    ./D:/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# |    ./tse_pkg.vhd syn, sim
+# |    ./eth_layers_pkg.vhd syn, sim
+# |    ./eth_pkg.vhd syn, sim
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | request TCL package from ACDS 10.0
+# | 
+package require -exact sopc 10.0
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | module avs2_eth_coe
+# | 
+set_module_property DESCRIPTION "MM slave port to conduit for the ETH module"
+set_module_property NAME avs2_eth_coe
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property GROUP Uniboard
+set_module_property AUTHOR ASTRON
+set_module_property DISPLAY_NAME avs2_eth_coe
+set_module_property TOP_LEVEL_HDL_FILE avs2_eth_coe.vhd
+set_module_property TOP_LEVEL_HDL_MODULE avs2_eth_coe
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property ANALYZE_HDL TRUE
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | files
+# | 
+add_file avs2_eth_coe.vhd {SYNTHESIS SIMULATION}
+add_file ../../../common/src/vhdl/common_pkg.vhd {SYNTHESIS SIMULATION}
+add_file ../../../dp/src/vhdl/dp_stream_pkg.vhd {SYNTHESIS SIMULATION}
+add_file tse_pkg.vhd {SYNTHESIS SIMULATION}
+add_file eth_layers_pkg.vhd {SYNTHESIS SIMULATION}
+add_file eth_pkg.vhd {SYNTHESIS SIMULATION}
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | parameters
+# | 
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | display items
+# | 
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point mm
+# | 
+add_interface mm clock end
+
+set_interface_property mm ENABLED true
+
+add_interface_port mm csi_mm_reset reset Input 1
+add_interface_port mm csi_mm_clk clk Input 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point mms_tse
+# | 
+add_interface mms_tse avalon end
+set_interface_property mms_tse addressAlignment DYNAMIC
+set_interface_property mms_tse associatedClock mm
+set_interface_property mms_tse burstOnBurstBoundariesOnly false
+set_interface_property mms_tse explicitAddressSpan 0
+set_interface_property mms_tse holdTime 0
+set_interface_property mms_tse isMemoryDevice false
+set_interface_property mms_tse isNonVolatileStorage false
+set_interface_property mms_tse linewrapBursts false
+set_interface_property mms_tse maximumPendingReadTransactions 0
+set_interface_property mms_tse printableDevice false
+set_interface_property mms_tse readLatency 0
+set_interface_property mms_tse readWaitTime 1
+set_interface_property mms_tse setupTime 0
+set_interface_property mms_tse timingUnits Cycles
+set_interface_property mms_tse writeWaitTime 0
+
+set_interface_property mms_tse ASSOCIATED_CLOCK mm
+set_interface_property mms_tse ENABLED true
+
+add_interface_port mms_tse mms_tse_address address Input 10
+add_interface_port mms_tse mms_tse_write write Input 1
+add_interface_port mms_tse mms_tse_read read Input 1
+add_interface_port mms_tse mms_tse_writedata writedata Input 32
+add_interface_port mms_tse mms_tse_readdata readdata Output 32
+add_interface_port mms_tse mms_tse_waitrequest waitrequest Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point mms_reg
+# | 
+add_interface mms_reg avalon end
+set_interface_property mms_reg addressAlignment DYNAMIC
+set_interface_property mms_reg associatedClock mm
+set_interface_property mms_reg burstOnBurstBoundariesOnly false
+set_interface_property mms_reg explicitAddressSpan 0
+set_interface_property mms_reg holdTime 0
+set_interface_property mms_reg isMemoryDevice false
+set_interface_property mms_reg isNonVolatileStorage false
+set_interface_property mms_reg linewrapBursts false
+set_interface_property mms_reg maximumPendingReadTransactions 0
+set_interface_property mms_reg printableDevice false
+set_interface_property mms_reg readLatency 1
+set_interface_property mms_reg readWaitStates 0
+set_interface_property mms_reg readWaitTime 0
+set_interface_property mms_reg setupTime 0
+set_interface_property mms_reg timingUnits Cycles
+set_interface_property mms_reg writeWaitTime 0
+
+set_interface_property mms_reg ASSOCIATED_CLOCK mm
+set_interface_property mms_reg ENABLED true
+
+add_interface_port mms_reg mms_reg_address address Input 4
+add_interface_port mms_reg mms_reg_write write Input 1
+add_interface_port mms_reg mms_reg_read read Input 1
+add_interface_port mms_reg mms_reg_writedata writedata Input 32
+add_interface_port mms_reg mms_reg_readdata readdata Output 32
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point mms_ram
+# | 
+add_interface mms_ram avalon end
+set_interface_property mms_ram addressAlignment DYNAMIC
+set_interface_property mms_ram associatedClock mm
+set_interface_property mms_ram burstOnBurstBoundariesOnly false
+set_interface_property mms_ram explicitAddressSpan 0
+set_interface_property mms_ram holdTime 0
+set_interface_property mms_ram isMemoryDevice false
+set_interface_property mms_ram isNonVolatileStorage false
+set_interface_property mms_ram linewrapBursts false
+set_interface_property mms_ram maximumPendingReadTransactions 0
+set_interface_property mms_ram printableDevice false
+set_interface_property mms_ram readLatency 2
+set_interface_property mms_ram readWaitStates 0
+set_interface_property mms_ram readWaitTime 0
+set_interface_property mms_ram setupTime 0
+set_interface_property mms_ram timingUnits Cycles
+set_interface_property mms_ram writeWaitTime 0
+
+set_interface_property mms_ram ASSOCIATED_CLOCK mm
+set_interface_property mms_ram ENABLED true
+
+add_interface_port mms_ram mms_ram_address address Input 10
+add_interface_port mms_ram mms_ram_write write Input 1
+add_interface_port mms_ram mms_ram_read read Input 1
+add_interface_port mms_ram mms_ram_writedata writedata Input 32
+add_interface_port mms_ram mms_ram_readdata readdata Output 32
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point interrupt
+# | 
+add_interface interrupt interrupt end
+set_interface_property interrupt associatedAddressablePoint mms_reg
+set_interface_property interrupt associatedClock mm
+
+set_interface_property interrupt ASSOCIATED_CLOCK mm
+set_interface_property interrupt ENABLED true
+
+add_interface_port interrupt ins_interrupt_irq irq Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point reset
+# | 
+add_interface reset conduit end
+
+set_interface_property reset ENABLED true
+
+add_interface_port reset coe_reset_export export Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point clk
+# | 
+add_interface clk conduit end
+
+set_interface_property clk ENABLED true
+
+add_interface_port clk coe_clk_export export Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point tse_address
+# | 
+add_interface tse_address conduit end
+
+set_interface_property tse_address ENABLED true
+
+add_interface_port tse_address coe_tse_address_export export Output 10
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point tse_write
+# | 
+add_interface tse_write conduit end
+
+set_interface_property tse_write ENABLED true
+
+add_interface_port tse_write coe_tse_write_export export Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point tse_read
+# | 
+add_interface tse_read conduit end
+
+set_interface_property tse_read ENABLED true
+
+add_interface_port tse_read coe_tse_read_export export Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point tse_writedata
+# | 
+add_interface tse_writedata conduit end
+
+set_interface_property tse_writedata ENABLED true
+
+add_interface_port tse_writedata coe_tse_writedata_export export Output 32
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point tse_readdata
+# | 
+add_interface tse_readdata conduit end
+
+set_interface_property tse_readdata ENABLED true
+
+add_interface_port tse_readdata coe_tse_readdata_export export Input 32
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point tse_waitrequest
+# | 
+add_interface tse_waitrequest conduit end
+
+set_interface_property tse_waitrequest ENABLED true
+
+add_interface_port tse_waitrequest coe_tse_waitrequest_export export Input 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point reg_address
+# | 
+add_interface reg_address conduit end
+
+set_interface_property reg_address ENABLED true
+
+add_interface_port reg_address coe_reg_address_export export Output 4
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point reg_write
+# | 
+add_interface reg_write conduit end
+
+set_interface_property reg_write ENABLED true
+
+add_interface_port reg_write coe_reg_write_export export Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point reg_read
+# | 
+add_interface reg_read conduit end
+
+set_interface_property reg_read ENABLED true
+
+add_interface_port reg_read coe_reg_read_export export Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point reg_writedata
+# | 
+add_interface reg_writedata conduit end
+
+set_interface_property reg_writedata ENABLED true
+
+add_interface_port reg_writedata coe_reg_writedata_export export Output 32
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point reg_readdata
+# | 
+add_interface reg_readdata conduit end
+
+set_interface_property reg_readdata ENABLED true
+
+add_interface_port reg_readdata coe_reg_readdata_export export Input 32
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point ram_address
+# | 
+add_interface ram_address conduit end
+
+set_interface_property ram_address ENABLED true
+
+add_interface_port ram_address coe_ram_address_export export Output 10
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point ram_write
+# | 
+add_interface ram_write conduit end
+
+set_interface_property ram_write ENABLED true
+
+add_interface_port ram_write coe_ram_write_export export Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point ram_read
+# | 
+add_interface ram_read conduit end
+
+set_interface_property ram_read ENABLED true
+
+add_interface_port ram_read coe_ram_read_export export Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point ram_writedata
+# | 
+add_interface ram_writedata conduit end
+
+set_interface_property ram_writedata ENABLED true
+
+add_interface_port ram_writedata coe_ram_writedata_export export Output 32
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point ram_readdata
+# | 
+add_interface ram_readdata conduit end
+
+set_interface_property ram_readdata ENABLED true
+
+add_interface_port ram_readdata coe_ram_readdata_export export Input 32
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point irq
+# | 
+add_interface irq conduit end
+
+set_interface_property irq ENABLED true
+
+add_interface_port irq coe_irq_export export Input 1
+# | 
+# +-----------------------------------

libraries/io/eth/src/vhdl/avs2_eth_hw.tcl

+# TCL File Generated by Component Editor 11.1sp2
+# Fri Jun 13 11:21:23 CEST 2014
+# DO NOT MODIFY
+
+
+# +-----------------------------------
+# | 
+# | avs2_eth "avs2_eth" v1.0
+# | ASTRON 2014.06.13.11:21:23
+# | 1GbE module
+# | 
+# | /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/avs2_eth.vhd
+# | 
+# |    ./avs2_eth.vhd syn, sim
+# |    ./eth_layers_pkg.vhd syn, sim
+# |    ./eth_pkg.vhd syn, sim
+# |    ./eth_checksum.vhd syn, sim
+# |    ./eth_crc_ctrl.vhd syn, sim
+# |    ./eth_crc_word.vhd syn, sim
+# |    ./eth_hdr_status.vhd syn, sim
+# |    ./eth_hdr_store.vhd syn, sim
+# |    ./eth_hdr_ctrl.vhd syn, sim
+# |    ./eth_hdr.vhd syn, sim
+# |    ./eth_buffer.vhd syn, sim
+# |    ./eth_udp_channel.vhd syn, sim
+# |    ./eth_control.vhd syn, sim
+# |    ./eth_mm_registers.vhd syn, sim
+# |    ./eth_mm_reg_frame.vhd syn, sim
+# |    ./eth_ihl_to_20.vhd syn, sim
+# |    ./eth.vhd syn, sim
+# |    ./tse_pkg.vhd syn, sim
+# |    ./tse.vhd syn, sim
+# |    ./tse_a_stratix4.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/tse_sgmii_lvds/tse_sgmii_lvds.vho sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/tse_sgmii_lvds/tse_sgmii_lvds.vhd syn
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/tse_sgmii_lvds/tse_sgmii_lvds.qip syn
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/tse_sgmii_gx/tse_sgmii_gx.vho sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/tse_sgmii_gx/tse_sgmii_gx.vhd syn
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/tse_sgmii_gx/tse_sgmii_gx.qip syn
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/fifo_sc/fifo_sc.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/mem/ram_crw_crw.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/mem/ram_cr_cw.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_eop_extend.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_validate.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_hold_ctrl.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_hold_data.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_pipeline.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_latency_increase.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_latency_adapter.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_fifo_sc.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_frame_rd.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_hold_input.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_shiftreg.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_fifo_fill.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_mux.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_demux.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_packet_detect.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_pkg.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_fifo_sc.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_fifo_sc_a_stratix4.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_mem_pkg.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_crw_crw_a_stratix4.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_crw_crw.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_rw_rw_a_str.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_rw_rw.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_reg_cross_domain.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_reg_r_w.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_spulse.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_switch.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_areset.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_async.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_pipeline.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_evt.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/gxb/v101/gx_reconfig_4.qip syn
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/gxb/v101/gx_reconfig_4.vhd syn, sim
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | request TCL package from ACDS 11.0
+# | 
+package require -exact sopc 11.0
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | module avs2_eth
+# | 
+set_module_property DESCRIPTION "1GbE module"
+set_module_property NAME avs2_eth
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP Uniboard
+set_module_property AUTHOR ASTRON
+set_module_property DISPLAY_NAME avs2_eth
+set_module_property TOP_LEVEL_HDL_FILE avs2_eth.vhd
+set_module_property TOP_LEVEL_HDL_MODULE avs2_eth
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property ANALYZE_HDL TRUE
+set_module_property STATIC_TOP_LEVEL_MODULE_NAME ""
+set_module_property FIX_110_VIP_PATH false
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | files
+# | 
+add_file avs2_eth.vhd {SYNTHESIS SIMULATION}
+add_file eth_layers_pkg.vhd {SYNTHESIS SIMULATION}
+add_file eth_pkg.vhd {SYNTHESIS SIMULATION}
+add_file eth_checksum.vhd {SYNTHESIS SIMULATION}
+add_file eth_crc_ctrl.vhd {SYNTHESIS SIMULATION}
+add_file eth_crc_word.vhd {SYNTHESIS SIMULATION}
+add_file eth_hdr_status.vhd {SYNTHESIS SIMULATION}
+add_file eth_hdr_store.vhd {SYNTHESIS SIMULATION}
+add_file eth_hdr_ctrl.vhd {SYNTHESIS SIMULATION}
+add_file eth_hdr.vhd {SYNTHESIS SIMULATION}
+add_file eth_buffer.vhd {SYNTHESIS SIMULATION}
+add_file eth_udp_channel.vhd {SYNTHESIS SIMULATION}
+add_file eth_control.vhd {SYNTHESIS SIMULATION}
+add_file eth_mm_registers.vhd {SYNTHESIS SIMULATION}
+add_file eth_mm_reg_frame.vhd {SYNTHESIS SIMULATION}
+add_file eth_ihl_to_20.vhd {SYNTHESIS SIMULATION}
+add_file eth.vhd {SYNTHESIS SIMULATION}
+add_file tse_pkg.vhd {SYNTHESIS SIMULATION}
+add_file tse.vhd {SYNTHESIS SIMULATION}
+add_file tse_a_stratix4.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/tse_sgmii_lvds/tse_sgmii_lvds.vho SIMULATION
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/tse_sgmii_lvds/tse_sgmii_lvds.vhd SYNTHESIS
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/tse_sgmii_lvds/tse_sgmii_lvds.qip SYNTHESIS
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/tse_sgmii_gx/tse_sgmii_gx.vho SIMULATION
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/tse_sgmii_gx/tse_sgmii_gx.vhd SYNTHESIS
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/tse_sgmii_gx/tse_sgmii_gx.qip SYNTHESIS
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/fifo_sc/fifo_sc.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/mem/ram_crw_crw.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/mem/ram_cr_cw.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_stream_pkg.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_eop_extend.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_validate.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_hold_ctrl.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_hold_data.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_pipeline.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_latency_increase.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_latency_adapter.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_fifo_sc.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_frame_rd.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_hold_input.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_shiftreg.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_fifo_fill.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_mux.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_demux.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_packet_detect.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_pkg.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_fifo_sc.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_fifo_sc_a_stratix4.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_mem_pkg.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_crw_crw_a_stratix4.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_crw_crw.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_rw_rw_a_str.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_rw_rw.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_reg_cross_domain.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_reg_r_w.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_spulse.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_switch.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_areset.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_async.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_pipeline.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_evt.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/gxb/v101/gx_reconfig_4.qip SYNTHESIS
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/MegaWizard/gxb/v101/gx_reconfig_4.vhd {SYNTHESIS SIMULATION}
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | parameters
+# | 
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | display items
+# | 
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point mm
+# | 
+add_interface mm clock end
+set_interface_property mm clockRate 0
+
+set_interface_property mm ENABLED true
+
+add_interface_port mm csi_mm_clk clk Input 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point mm_reset
+# | 
+add_interface mm_reset reset end
+set_interface_property mm_reset associatedClock mm
+set_interface_property mm_reset synchronousEdges DEASSERT
+
+set_interface_property mm_reset ENABLED true
+
+add_interface_port mm_reset csi_mm_reset reset Input 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point mms_tse
+# | 
+add_interface mms_tse avalon end
+set_interface_property mms_tse addressAlignment DYNAMIC
+set_interface_property mms_tse addressUnits WORDS
+set_interface_property mms_tse associatedClock mm
+set_interface_property mms_tse associatedReset mm_reset
+set_interface_property mms_tse burstOnBurstBoundariesOnly false
+set_interface_property mms_tse explicitAddressSpan 0
+set_interface_property mms_tse holdTime 0
+set_interface_property mms_tse isMemoryDevice false
+set_interface_property mms_tse isNonVolatileStorage false
+set_interface_property mms_tse linewrapBursts false
+set_interface_property mms_tse maximumPendingReadTransactions 0
+set_interface_property mms_tse printableDevice false
+set_interface_property mms_tse readLatency 0
+set_interface_property mms_tse readWaitStates 0
+set_interface_property mms_tse readWaitTime 0
+set_interface_property mms_tse setupTime 0
+set_interface_property mms_tse timingUnits Cycles
+set_interface_property mms_tse writeWaitTime 0
+
+set_interface_property mms_tse ENABLED true
+
+add_interface_port mms_tse mms_tse_address address Input 10
+add_interface_port mms_tse mms_tse_write write Input 1
+add_interface_port mms_tse mms_tse_read read Input 1
+add_interface_port mms_tse mms_tse_writedata writedata Input 32
+add_interface_port mms_tse mms_tse_readdata readdata Output 32
+add_interface_port mms_tse mms_tse_waitrequest waitrequest Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point mms_reg
+# | 
+add_interface mms_reg avalon end
+set_interface_property mms_reg addressAlignment DYNAMIC
+set_interface_property mms_reg addressUnits WORDS
+set_interface_property mms_reg associatedClock mm
+set_interface_property mms_reg associatedReset mm_reset
+set_interface_property mms_reg burstOnBurstBoundariesOnly false
+set_interface_property mms_reg explicitAddressSpan 0
+set_interface_property mms_reg holdTime 0
+set_interface_property mms_reg isMemoryDevice false
+set_interface_property mms_reg isNonVolatileStorage false
+set_interface_property mms_reg linewrapBursts false
+set_interface_property mms_reg maximumPendingReadTransactions 0
+set_interface_property mms_reg printableDevice false
+set_interface_property mms_reg readLatency 1
+set_interface_property mms_reg readWaitStates 0
+set_interface_property mms_reg readWaitTime 0
+set_interface_property mms_reg setupTime 0
+set_interface_property mms_reg timingUnits Cycles
+set_interface_property mms_reg writeWaitTime 0
+
+set_interface_property mms_reg ENABLED true
+
+add_interface_port mms_reg mms_reg_address address Input 4
+add_interface_port mms_reg mms_reg_write write Input 1
+add_interface_port mms_reg mms_reg_read read Input 1
+add_interface_port mms_reg mms_reg_writedata writedata Input 32
+add_interface_port mms_reg mms_reg_readdata readdata Output 32
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point mms_ram
+# | 
+add_interface mms_ram avalon end
+set_interface_property mms_ram addressAlignment DYNAMIC
+set_interface_property mms_ram addressUnits WORDS
+set_interface_property mms_ram associatedClock mm
+set_interface_property mms_ram associatedReset mm_reset
+set_interface_property mms_ram burstOnBurstBoundariesOnly false
+set_interface_property mms_ram explicitAddressSpan 0
+set_interface_property mms_ram holdTime 0
+set_interface_property mms_ram isMemoryDevice false
+set_interface_property mms_ram isNonVolatileStorage false
+set_interface_property mms_ram linewrapBursts false
+set_interface_property mms_ram maximumPendingReadTransactions 0
+set_interface_property mms_ram printableDevice false
+set_interface_property mms_ram readLatency 2
+set_interface_property mms_ram readWaitStates 0
+set_interface_property mms_ram readWaitTime 0
+set_interface_property mms_ram setupTime 0
+set_interface_property mms_ram timingUnits Cycles
+set_interface_property mms_ram writeWaitTime 0
+
+set_interface_property mms_ram ENABLED true
+
+add_interface_port mms_ram mms_ram_address address Input 10
+add_interface_port mms_ram mms_ram_write write Input 1
+add_interface_port mms_ram mms_ram_read read Input 1
+add_interface_port mms_ram mms_ram_writedata writedata Input 32
+add_interface_port mms_ram mms_ram_readdata readdata Output 32
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point interrupt
+# | 
+add_interface interrupt interrupt end
+set_interface_property interrupt associatedAddressablePoint mms_reg
+set_interface_property interrupt associatedClock mm
+set_interface_property interrupt associatedReset mm_reset
+
+set_interface_property interrupt ENABLED true
+
+add_interface_port interrupt ins_interrupt_irq irq Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point eth_clk
+# | 
+add_interface eth_clk conduit end
+
+set_interface_property eth_clk ENABLED true
+
+add_interface_port eth_clk coe_eth_clk_export export Input 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point eth_txp
+# | 
+add_interface eth_txp conduit end
+
+set_interface_property eth_txp ENABLED true
+
+add_interface_port eth_txp coe_eth_txp_export export Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point eth_rxp
+# | 
+add_interface eth_rxp conduit end
+
+set_interface_property eth_rxp ENABLED true
+
+add_interface_port eth_rxp coe_eth_rxp_export export Input 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point led_an
+# | 
+add_interface led_an conduit end
+
+set_interface_property led_an ENABLED true
+
+add_interface_port led_an coe_led_an_export export Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point led_link
+# | 
+add_interface led_link conduit end
+
+set_interface_property led_link ENABLED true
+
+add_interface_port led_link coe_led_link_export export Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point led_disp_err
+# | 
+add_interface led_disp_err conduit end
+
+set_interface_property led_disp_err ENABLED true
+
+add_interface_port led_disp_err coe_led_disp_err_export export Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point led_char_err
+# | 
+add_interface led_char_err conduit end
+
+set_interface_property led_char_err ENABLED true
+
+add_interface_port led_char_err coe_led_char_err_export export Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point led_crs
+# | 
+add_interface led_crs conduit end
+
+set_interface_property led_crs ENABLED true
+
+add_interface_port led_crs coe_led_crs_export export Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point led_col
+# | 
+add_interface led_col conduit end
+
+set_interface_property led_col ENABLED true
+
+add_interface_port led_col coe_led_col_export export Output 1
+# | 
+# +-----------------------------------