Corrected timing of valid in_dat and ref_dat_arr in p_diff_arr and...

Corrected timing of valid in_dat and ref_dat_arr in p_diff_arr and p_diff_detect. Explained difference between g_use_steps is TRUE and FALSE regarding the calculation of ref_dat.

libraries/base/diag/src/vhdl/diag_rx_seq.vhd

@@ -72,10 +72,20 @@
 --   Data errors that match a step size cannot be detected. However if such
 --   an error occurs then typically the next increment will cause a mismatch.
 --
---   The feature of being able to detect errors per bit as with g_use_steps=
+-- Remarks:
+-- . The feature of being able to detect errors per bit as with g_use_steps=
 --   FALSE is not supported when g_use_steps=TRUE. Therefore the
---   diag_res[g_dat_w-1:0] = -1 (ll '1') when a difference occurs that is no
---   in diag_steps_arr. 
+--   diag_res[g_dat_w-1:0] = -1 (all '1') when a difference occurs that is no
+--   in diag_steps_arr.
+-- . The common_lfsr_nxt_seq() that is used when g_use_steps=FALSE uses the
+--   in_dat_reg as initialization value for the reference sequence. All
+--   subsequent values are derived when in_val_reg='1'. This is possible
+--   because given a first value all subsequent values for PSRG or COUNTER
+--   with +1 increment are known. For g_use_steps=TRUE the sequence is not
+--   known in advance because different increment steps can occur at 
+--   arbitrary instants. Therefore then the in_dat_reg input is also used 
+--   during the sequence, to determine all g_nof_steps next values are correct
+--   in case they occur.
 
 LIBRARY IEEE, common_lib;
 USE IEEE.std_logic_1164.ALL;
@@ -164,11 +174,11 @@ ARCHITECTURE rtl OF diag_rx_seq IS
 
   TYPE t_dat_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
   
-  SIGNAL ref_dat_arr      : t_dat_arr(g_nof_steps-1 DOWNTO 0);
+  SIGNAL ref_dat_arr      : t_dat_arr(g_nof_steps-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
   SIGNAL nxt_ref_dat_arr  : t_dat_arr(g_nof_steps-1 DOWNTO 0);
-  SIGNAL diff_arr         : STD_LOGIC_VECTOR(g_nof_steps-1 DOWNTO 0);
+  SIGNAL diff_arr         : STD_LOGIC_VECTOR(g_nof_steps-1 DOWNTO 0) := (OTHERS=>'0');
   SIGNAL nxt_diff_arr     : STD_LOGIC_VECTOR(g_nof_steps-1 DOWNTO 0);
-  SIGNAL diff_detect      : STD_LOGIC;
+  SIGNAL diff_detect      : STD_LOGIC := '0';
   SIGNAL nxt_diff_detect  : STD_LOGIC;
   SIGNAL diff_hold        : STD_LOGIC;
   
@@ -282,7 +292,7 @@ BEGIN
     common_lfsr_nxt_seq(c_lfsr_nr,    -- IN
                         ref_en,       -- IN
                         in_val_reg,   -- IN, use in_val_reg to allow gaps in the input data valid stream
-                        in_dat_reg,   -- IN
+                        in_dat_reg,   -- IN, used only to init nxt_prsg and nxt_cntr when ref_en='0'
                         prsg,         -- IN
                         cntr,         -- IN
                         nxt_prsg,     -- OUT
@@ -336,25 +346,25 @@ BEGIN
       END IF;
     END PROCESS;
         
-    -- Detect difference for each step.  The ref_dat_arr has latency 1 compared to the input dat
-    p_diff_arr : PROCESS(diff_arr, in_val_dly1, in_dat_dly1, ref_dat_arr)
+    -- Detect difference for each allowed reference data.
+    p_diff_arr : PROCESS(diff_arr, in_val_reg, in_dat_reg, ref_dat_arr)
     BEGIN
       nxt_diff_arr <= diff_arr;
-      IF in_val_dly1='1' THEN
+      IF in_val_reg='1' THEN
         nxt_diff_arr <= (OTHERS=>'1');
         FOR I IN g_nof_steps-1 DOWNTO 0 LOOP
-          IF UNSIGNED(ref_dat_arr(I))=UNSIGNED(in_dat_dly1) THEN
+          IF UNSIGNED(ref_dat_arr(I))=UNSIGNED(in_dat_reg) THEN
             nxt_diff_arr(I) <= '0';
           END IF;
         END LOOP;
       END IF;
     END PROCESS;
     
-    -- detect diff when no step counter value matches
-    p_diff_detect : PROCESS(diff_detect, diff_arr, in_val_dly2)
+    -- detect diff when none of the step counter value matches
+    p_diff_detect : PROCESS(diff_detect, diff_arr, in_val_dly1)
     BEGIN
       nxt_diff_detect <= diff_detect;
-      IF in_val_dly2='1' THEN
+      IF in_val_dly1='1' THEN
         nxt_diff_detect <= '0';
         IF vector_and(diff_arr)='1' THEN
           nxt_diff_detect <= '1';
@@ -362,7 +372,7 @@ BEGIN
       END IF;
     END PROCESS;
     
-    -- hold detected diff value
+    -- hold detected diff detect
     u_dat : ENTITY common_lib.common_switch
     PORT MAP(
       clk         => clk,
@@ -372,7 +382,7 @@ BEGIN
       out_level   => diff_hold
     );
     
-    diff_dat <= (OTHERS=> diff_hold);
+    diff_res <= (OTHERS=> diff_hold);  -- convert diff_hold to diff_res slv format as used for g_use_steps=FALSE
   END GENERATE;