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Commit a43cb721 authored by Pieter Donker's avatar Pieter Donker
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L2SDP-52: changes in yaml files.

parent 1e9c1d03
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2 merge requests!28Master,!22Resolve L2SDP-52
......@@ -7,20 +7,24 @@ fpga_name : unb2b_minimal
fpga_description: "unb2b_minimal system"
peripherals:
- peripheral_name: unb2b_board/system
slave_port_names:
- pio_system_info
lock_base_address: 0x0
- peripheral_name: unb2b_board/rom_system
- peripheral_name: unb2b_board/unb2b
slave_port_names:
- rom_system_info
lock_base_address: 0x10000
- peripheral_name: unb2b_board/ctrl
slave_port_names:
- pio_system_info
- pio_wdi
- peripheral_name: unb2b_board/wdi
slave_port_names:
- reg_wdi
- reg_unb_sens
- reg_unb_pmbus
- reg_fpga_temp_sens
- reg_fpga_voltage_sens
parameter_overrides:
- { name : g_sim, value: FALSE }
- { name : g_clk_freq, value: 125E6 }
- { name : g_temp_high, value: 85 }
#lock_base_address: 0x0
#lock_base_address: 0x4000
- peripheral_name: eth/eth1g
slave_port_names:
- avs_eth_0_tse
......@@ -41,20 +45,4 @@ peripherals:
- peripheral_name: remu/remu
slave_port_names:
- reg_remu
- peripheral_name: unb2b_board/sens
slave_port_names:
- reg_unb_sens
- reg_unb_pmbus
parameter_overrides:
- { name : g_sim, value: FALSE }
- { name : g_clk_freq, value: 125E6 }
- { name : g_temp_high, value: 85 }
\ No newline at end of file
- peripheral_name: unb2b_board/fpga_sens
slave_port_names:
- reg_fpga_temp_sens
- reg_fpga_voltage_sens
parameter_overrides:
- { name : g_sim, value: FALSE }
- { name : g_clk_freq, value: 125E6 }
- { name : g_temp_high, value: 85 }
---
schema_name: args
schema_version: 1.0
schema_type: peripheral
......@@ -8,10 +9,16 @@ hdl_library_description: " This is the description for the unb2b_board package "
# <peripheral_group>_<peripheral_name>_<slave_name>_<slave_type>
peripherals:
- peripheral_name: rom_system
- peripheral_name: unb2b
parameters:
- { name: g_sim, value: FALSE }
- { name: g_clk_freq, value: c_unb2b_board_mm_clk_freq_125M }
- { name: g_temp_high, value: 85 }
slave_ports:
# rom_system_info
- slave_name : info
- slave_name : rom_system
slave_type : REG
fields:
- - field_name : info
......@@ -22,13 +29,8 @@ peripherals:
"address place for rom_system_info"
slave_description: " rom_info "
peripheral_description: |
" settings for rom_system_info register "
- peripheral_name: system
slave_ports:
# reg_system_info
- slave_name : info
- slave_name : system
slave_type : REG
fields:
- - field_name : info
......@@ -39,15 +41,8 @@ peripherals:
"address place for reg_system_info"
slave_description: " reg_info "
peripheral_description: |
" settings for reg_system_info register "
# peripheral, unb2b_board_wdi_reg
- peripheral_name: ctrl
slave_ports:
# actual hdl name: unb2b_board_wdi_reg
- slave_name : pio_wdi
- slave_name : ctrl
slave_type : REG
fields:
- - field_name : nios_reset
......@@ -59,12 +54,6 @@ peripherals:
slave_description: "Reset register, for nios "
peripheral_description: " "
# peripheral, unb2b_board_wdi_reg
- peripheral_name: wdi
slave_ports:
# actual hdl name: unb2b_board_wdi_reg
- slave_name : wdi
slave_type : REG
......@@ -76,34 +65,21 @@ peripherals:
slave_description: "Reset register, if the right value is provided the factory image will be reloaded "
peripheral_description: " "
# periheral, unb2b_board_sens
- peripheral_name: sens
parameters:
- { name: g_sim, value: FALSE }
- { name: g_clk_freq, value: c_unb2b_board_mm_clk_freq_125M }
- { name: g_temp_high, value: 85 }
slave_ports:
# actual hdl name: reg_unb2b_sens
- slave_name : sens
- slave_name : board_sens
slave_type : REG
fields:
- - field_name : data
- - field_name : sens
width : 32
access_mode : RO
address_offset: 0x00
number_of_fields: 40
field_description: ""
slave_description: " "
# actual hdl name: reg_unb2b_pmbus
- slave_name : pmbus
- slave_name : board_pmbus
slave_type : REG
fields:
- - field_name : data
- - field_name : pmbus
width : 32
access_mode : RO
address_offset: 0x00
......@@ -111,36 +87,21 @@ peripherals:
field_description: ""
slave_description: " "
peripheral_description: |
"
"
# periheral, unb2b_board_sens
- peripheral_name: fpga_sens
parameters:
- { name: g_sim, value: FALSE }
- { name: g_clk_freq, value: c_unb2b_board_mm_clk_freq_125M }
- { name: g_temp_high, value: 85 }
slave_ports:
# actual hdl name: reg_unb2b_sens
- slave_name : temp
- slave_name : fpga_temp
slave_type : REG
fields:
- - field_name : data
- - field_name : temp
width : 32
access_mode : RO
address_offset: 0x00
number_of_fields: 1
field_description: ""
slave_description: " "
# actual hdl name: reg_unb2b_sens
- slave_name : voltage
- slave_name : fpga_voltage
slave_type : REG
fields:
- - field_name : data
- - field_name : voltage
width : 32
access_mode : RO
address_offset: 0x00
......
......@@ -71,11 +71,11 @@ peripherals:
field_description: " "
- slave_name : DPMM_DATA
slave_type : REG
slave_type : FIFO
fields:
- - field_name : data
width : 32
access_mode : RW
access_mode : RO
address_offset: 0x0
number_of_fields: 1
field_description: " "
......@@ -92,11 +92,11 @@ peripherals:
field_description: " "
- slave_name : MMDP_DATA
slave_type : REG
slave_type : FIFO
fields:
- - field_name : data
width : 32
access_mode : RW
access_mode : WO
address_offset: 0x0
number_of_fields: 2
field_description: " "
......
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