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Commit a37d3857 authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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update using *

parent 06018018
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boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ 11
− 4
View file @ a37d3857
...@@ -40,6 +40,7 @@ set_clock_groups -asynchronous -group {CLKUSR} ...@@ -40,6 +40,7 @@ set_clock_groups -asynchronous -group {CLKUSR}
set_clock_groups -asynchronous -group {SA_CLK} set_clock_groups -asynchronous -group {SA_CLK}
set_clock_groups -asynchronous -group {SB_CLK} set_clock_groups -asynchronous -group {SB_CLK}
# IOPLL outputs (which have global names defined in the IP qsys settings)
set_clock_groups -asynchronous -group [get_clocks pll_clk20] set_clock_groups -asynchronous -group [get_clocks pll_clk20]
set_clock_groups -asynchronous -group [get_clocks pll_clk50] set_clock_groups -asynchronous -group [get_clocks pll_clk50]
set_clock_groups -asynchronous -group [get_clocks pll_clk100] set_clock_groups -asynchronous -group [get_clocks pll_clk100]
...@@ -49,15 +50,21 @@ set_clock_groups -asynchronous -group [get_clocks pll_clk200p] ...@@ -49,15 +50,21 @@ set_clock_groups -asynchronous -group [get_clocks pll_clk200p]
set_clock_groups -asynchronous -group [get_clocks pll_clk400] set_clock_groups -asynchronous -group [get_clocks pll_clk400]
set_clock_groups -asynchronous -group [get_clocks {u_revision|u_ctrl|\gen_mm_clk_hardware:u_unb2_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk3}] #set_clock_groups -asynchronous -group [get_clocks {u_revision|u_ctrl|\gen_mm_clk_hardware:u_unb2_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk3}]
set_clock_groups -asynchronous -group [get_clocks {u_revision|u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}] #set_clock_groups -asynchronous -group [get_clocks {u_revision|u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
set_clock_groups -asynchronous -group [get_clocks {*u_ctrl|\gen_mm_clk_hardware:u_unb2_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk3}]
set_clock_groups -asynchronous -group [get_clocks {*u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
# unb2_minimal
set_clock_groups -asynchronous -group [get_clocks {*u_ctrl|\gen_mm_clk_hardware:u_unb2_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}]
#set_clock_groups -asynchronous -group [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_tr_10GbE_0|u_tech_eth_10g|\gen_ip_arria10:u0|u_tech_10gbase_r|\gen_ip_arria10:u0|\gen_phy_12:u_ip_arria10_phy_10gbase_r_12|xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk}] set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_tr_10GbE_0|u_tech_eth_10g|\gen_ip_arria10:u0|u_tech_10gbase_r|\gen_ip_arria10:u0|\gen_phy_12:u_ip_arria10_phy_10gbase_r_12|xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk}]
set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}] set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}] set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}]
set_clock_groups -asynchronous -group [get_clocks {u_ctrl|\gen_mm_clk_hardware:u_unb2_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}]
set_clock_groups -asynchronous -group [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
#set_clock_groups -asynchronous \ #set_clock_groups -asynchronous \
#-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \ #-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
......
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