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Commit a2eaacec authored by Eric Kooistra's avatar Eric Kooistra
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Merge branch 'L2SDP-850' into 'master' 

Resolve L2SDP-850

Closes L2SDP-850

See merge request desp/hdl!295
parents e6a478a5 a6d013e6
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1 merge request!295Resolve L2SDP-850
Pipeline #40637 passed
Stage: simulation
Stage: synthesis
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boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/hdllib.cfg 0 → 100644
+ 119
− 0
View file @ a2eaacec
hdl_lib_name = unb2c_test_ddr_16G
hdl_library_clause_name = unb2c_test_ddr_16G_lib
hdl_lib_uses_synth = common mm technology unb2c_board unb2c_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
hdl_lib_include_ip =
# Comment all IP that is not used in this design
# DDR memory
ip_arria10_e2sg_ddr4_16g_1600_64b
ip_arria10_e2sg_ddr4_16g_1600_72b
synth_files =
unb2c_test_ddr_16G.vhd
test_bench_files =
tb_unb2c_test_ddr_16G.vhd
regression_test_vhdl =
tb_unb2c_test_ddr_16G.vhd
[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
quartus .
../../quartus .
../../src/hex hex
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_pre_files =
quartus/unb2c_test_ddr_16G.sdc
$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_test_ddr_16G_pins.tcl
quartus_vhdl_files =
quartus_qip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr_16G/qsys_unb2c_test/qsys_unb2c_test.qip
quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd 0 → 100644
+ 38
− 0
View file @ a2eaacec
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, unb2c_test_lib;
USE IEEE.std_logic_1164.ALL;
ENTITY tb_unb2c_test_ddr_16G IS
END tb_unb2c_test_ddr_16G;
ARCHITECTURE tb OF tb_unb2c_test_ddr_16G IS
BEGIN
u_tb_unb2c_test : ENTITY unb2c_test_lib.tb_unb2c_test
GENERIC MAP (
g_design_name => "unb2c_test_ddr_16G"
);
END tb;
boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd 0 → 100644
+ 130
− 0
View file @ a2eaacec
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib, tech_ddr_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY unb2c_test_ddr_16G IS
GENERIC (
g_design_name : STRING := "unb2c_test_ddr_16G";
g_design_note : STRING := "DDR: MB I and II";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_revision_id : STRING := "" -- revision ID -- set by QSF
);
PORT (
-- GENERAL
CLK : IN STD_LOGIC; -- System Clock
PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
VERSION : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0);
ID : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0);
TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
-- DDR reference clocks
MB_I_REF_CLK : IN STD_LOGIC; -- Reference clock for MB_I
MB_II_REF_CLK : IN STD_LOGIC; -- Reference clock for MB_II
-- SO-DIMM Memory Bank I
MB_I_IN : IN t_tech_ddr4_phy_in;
MB_I_IO : INOUT t_tech_ddr4_phy_io;
MB_I_OU : OUT t_tech_ddr4_phy_ou;
-- SO-DIMM Memory Bank II
MB_II_IN : IN t_tech_ddr4_phy_in;
MB_II_IO : INOUT t_tech_ddr4_phy_io;
MB_II_OU : OUT t_tech_ddr4_phy_ou;
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0)
);
END unb2c_test_ddr_16G;
ARCHITECTURE str OF unb2c_test_ddr_16G IS
BEGIN
u_revision : ENTITY unb2c_test_lib.unb2c_test
GENERIC MAP (
g_design_name => g_design_name,
g_design_note => g_design_note,
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
g_revision_id => g_revision_id
)
PORT MAP (
-- GENERAL
CLK => CLK,
PPS => PPS,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- Others
VERSION => VERSION,
ID => ID,
TESTIO => TESTIO,
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT,
-- DDR reference clocks
MB_I_REF_CLK => MB_I_REF_CLK,
MB_II_REF_CLK => MB_II_REF_CLK,
-- SO-DIMM Memory Bank I
MB_I_IN => MB_I_IN,
MB_I_IO => MB_I_IO,
MB_I_OU => MB_I_OU,
-- SO-DIMM Memory Bank II
MB_II_IN => MB_II_IN,
MB_II_IO => MB_II_IO,
MB_II_OU => MB_II_OU,
QSFP_LED => QSFP_LED
);
END str;
boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+ 1
− 1
View file @ a2eaacec
......@@ -180,7 +180,7 @@ ARCHITECTURE str OF unb2c_test IS
-- ddr
CONSTANT c_ddr_ctlr_data_w : NATURAL := func_tech_ddr_ctlr_data_w(c_ddr_MB_I); -- = 576, assume both MB_I and MB_II use the same ctlr_data_w
CONSTANT c_ddr_dp_data_w : NATURAL := 144; -- DDR4 with dq_w = 72, rsl = 8 so ctrl data width = 576 and therefore the mixed width FIFO ratio is 576 /144 = 4
CONSTANT c_ddr_dp_data_w : NATURAL := c_ddr_ctlr_data_w / 4; -- DDR4 with dq_w = 72, rsl = 8 so ctrl data width = 576 and therefore the mixed width FIFO ratio is 576 /144 = 4
CONSTANT c_ddr_dp_seq_dat_w : NATURAL := 16; -- >= 1, test sequence data width. Choose c_ddr_dp_seq_dat_w <= c_ddr_dp_data_w. The seq data gets replicated to fill c_ddr_dp_data_w.
CONSTANT c_ddr_dp_wr_fifo_depth : NATURAL := 256 * (c_ddr_ctlr_data_w/c_ddr_dp_data_w); -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) to make full use of M9K which have at least 256 words
CONSTANT c_ddr_dp_rd_fifo_depth : NATURAL := 256 * (c_ddr_ctlr_data_w/c_ddr_dp_data_w); -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) or factors of 2 more to fit max number of read bursts
......
boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
+ 2
− 0
View file @ a2eaacec
......@@ -84,6 +84,7 @@ PACKAGE unb2c_test_pkg IS
CONSTANT c_test_10GbE : t_unb2c_test_config := (FALSE,FALSE,FALSE, TRUE, TRUE,FALSE,FALSE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
CONSTANT c_test_10GbE_qb : t_unb2c_test_config := (FALSE,FALSE,FALSE, TRUE,FALSE, TRUE,FALSE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
CONSTANT c_test_ddr : t_unb2c_test_config := (FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE, TRUE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
CONSTANT c_test_ddr_16G : t_unb2c_test_config := (FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE, TRUE,FALSE,c_tech_ddr4_16g_1600m_64, c_tech_ddr4_16g_1600m_72_64);
CONSTANT c_test_heater : t_unb2c_test_config := (FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
CONSTANT c_test_jesd204b : t_unb2c_test_config := (FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
......@@ -103,6 +104,7 @@ PACKAGE BODY unb2c_test_pkg IS
ELSIF g_design_name = "unb2c_test_jesd204b" THEN RETURN c_test_jesd204b;
ELSIF g_design_name = "unb2c_test_1GbE_I" THEN RETURN c_test_1GbE_I_UDP;
ELSIF g_design_name = "unb2c_test_1GbE_II" THEN RETURN c_test_1GbE_II_UDP;
ELSIF g_design_name = "unb2c_test_ddr_16G" THEN RETURN c_test_ddr_16G;
ELSE RETURN c_test_minimal;
END IF;
END;
......
libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
+ 31
− 11
View file @ a2eaacec
......@@ -76,6 +76,7 @@ ARCHITECTURE str OF tech_ddr_arria10_e2sg IS
CONSTANT c_gigabytes : NATURAL := func_tech_ddr_module_size(g_tech_ddr);
CONSTANT c_ctlr_address_w : NATURAL := func_tech_ddr_ctlr_address_w(g_tech_ddr);
CONSTANT c_ctlr_ip_data_w : NATURAL := func_tech_ddr_ctlr_ip_data_w(g_tech_ddr);
CONSTANT c_ctlr_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr);
SIGNAL i_ctlr_gen_clk : STD_LOGIC;
......@@ -85,6 +86,10 @@ ARCHITECTURE str OF tech_ddr_arria10_e2sg IS
SIGNAL local_cal_success : STD_LOGIC;
SIGNAL local_cal_fail : STD_LOGIC;
SIGNAL amm_readdata : STD_LOGIC_VECTOR(c_ctlr_ip_data_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL amm_writedata : STD_LOGIC_VECTOR(c_ctlr_ip_data_w-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
ctlr_gen_clk <= i_ctlr_gen_clk;
......@@ -101,8 +106,8 @@ BEGIN
amm_read_0 => ctlr_mosi.rd, -- .read
amm_write_0 => ctlr_mosi.wr, -- .write
amm_address_0 => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address
amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata
amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata
amm_readdata_0 => ctlr_miso.rddata(c_ctlr_ip_data_w-1 DOWNTO 0), -- .readdata
amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_ip_data_w-1 DOWNTO 0), -- .writedata
amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
amm_byteenable_0 => (OTHERS=>'1'), -- .byteenable
amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
......@@ -155,8 +160,8 @@ BEGIN
amm_read_0 => ctlr_mosi.rd, -- .read
amm_write_0 => ctlr_mosi.wr, -- .write
amm_address_0 => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address
amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata
amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata
amm_readdata_0 => ctlr_miso.rddata(c_ctlr_ip_data_w-1 DOWNTO 0), -- .readdata
amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_ip_data_w-1 DOWNTO 0), -- .writedata
amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
amm_byteenable_0 => (OTHERS=>'1'), -- .byteenable
amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
......@@ -209,8 +214,8 @@ BEGIN
amm_read_0 => ctlr_mosi.rd, -- .read
amm_write_0 => ctlr_mosi.wr, -- .write
amm_address_0 => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address
amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata
amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata
amm_readdata_0 => ctlr_miso.rddata(c_ctlr_ip_data_w-1 DOWNTO 0), -- .readdata
amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_ip_data_w-1 DOWNTO 0), -- .writedata
amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
amm_byteenable_0 => (OTHERS=>'1'), -- .byteenable
amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
......@@ -263,8 +268,8 @@ BEGIN
amm_read_0 => ctlr_mosi.rd, -- .read
amm_write_0 => ctlr_mosi.wr, -- .write
amm_address_0 => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address
amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata
amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata
amm_readdata_0 => amm_readdata, -- .readdata
amm_writedata_0 => amm_writedata, -- .writedata
amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
amm_byteenable_0 => (OTHERS=>'1'), -- .byteenable
amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
......@@ -301,10 +306,25 @@ BEGIN
--local_init_done => ctlr_miso.done, -- status.local_init_done
-- local_init_done = ctlr_init_done originally and mapped to ctlr_miso.done for the DDR3 IP. For the DDR4 IP the local_cal_success and
-- NOT local_cal_fail seem to serve as local_init_done
gen_rewire_data : IF g_tech_ddr.mem_dq_w < g_tech_ddr.dq_w GENERATE -- Used when 64 bit modules are used in unb2c slot II as it only supports 72 bit IP (not 64 bit IP).
ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0) <= func_tech_ddr_rewire_72b_to_64b(g_tech_ddr, amm_readdata);
amm_writedata <= func_tech_ddr_rewire_64b_to_72b(g_tech_ddr, ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0));
ctlr_miso.done <= local_cal_success AND NOT local_cal_fail WHEN rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
ctlr_miso.done <= '1';
ctlr_miso.cal_ok <= '1';
ctlr_miso.cal_fail <= '0';
END GENERATE;
gen_no_rewire_data : IF g_tech_ddr.mem_dq_w = g_tech_ddr.dq_w GENERATE
ctlr_miso.rddata(c_ctlr_ip_data_w-1 DOWNTO 0) <= amm_readdata;
amm_writedata <= ctlr_mosi.wrdata(c_ctlr_ip_data_w-1 DOWNTO 0);
ctlr_miso.done <= local_cal_success AND NOT local_cal_fail WHEN rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
END GENERATE;
END GENERATE;
......
libraries/technology/ddr/tech_ddr_pkg.vhd
+ 54
− 27
View file @ a2eaacec
......@@ -57,6 +57,7 @@ PACKAGE tech_ddr_pkg IS
command_queue_depth : NATURAL; -- = 8
maxburstsize : NATURAL; -- = 64
maxburstsize_w : NATURAL; -- = 7 = ceil_log2(maxburstsize+1)
mem_dq_w : NATURAL; -- = 64 dq connected to the memory module, can be = dq_w or 64 whenn dq_w = 72
END RECORD;
FUNCTION func_tech_sel_ddr(g_technology : NATURAL; g_ddr3, g_ddr4 : t_c_tech_ddr) RETURN t_c_tech_ddr; -- Select DDR3 or DDR4 dependent on the technology
......@@ -65,43 +66,46 @@ PACKAGE tech_ddr_pkg IS
FUNCTION func_tech_ddr_dq_address_w( c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR address width for the DQ data at the PHY mts rate
FUNCTION func_tech_ddr_ctlr_address_w(c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR address width for the controller data at the by rsl=4 reduced rate
FUNCTION func_tech_ddr_ctlr_data_w( c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR data width for the controller data at the by rsl=4 reduced rate
FUNCTION func_tech_ddr_ctlr_ip_data_w(c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR data width for the controller data at the by rsl=4 reduced rate
FUNCTION func_tech_ddr_module_size( c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR module size in GByte
FUNCTION func_tech_ddr_sim_size(c_ddr : t_c_tech_ddr; sim_ctrl_addr_w : NATURAL) RETURN t_c_tech_ddr; -- derive sim_ddr from c_ddr (or alternatively use predefined c_tech_ddr*_sim)
FUNCTION func_tech_ddr_rewire_64b_to_72b(c_ddr : t_c_tech_ddr; vec_64b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
FUNCTION func_tech_ddr_rewire_72b_to_64b(c_ddr : t_c_tech_ddr; vec_72b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
-- a a cs cs
-- name mts master rank a row col ba dq dqs dm dbi bg ck cke w w_w odt term rsl rsl_w cqd burst burst_w
CONSTANT c_tech_ddr3_max : t_c_tech_ddr := ("none", 800, TRUE, "DUAL ", 16, 16, 11, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7); -- maximum ranges for record field definitions
-- name mts master rank a row col ba dq dqs dm dbi bg ck cke w w_w odt term rsl rsl_w cqd burst burst_w mem_dq_w
CONSTANT c_tech_ddr3_max : t_c_tech_ddr := ("none", 800, TRUE, "DUAL ", 16, 16, 11, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64); -- maximum ranges for record field definitions
-- use predefined c_tech_ddr3_sim or derive it using func_tech_ddr_sim_size()
CONSTANT c_tech_ddr3_sim_8k : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 10, 1, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
CONSTANT c_tech_ddr3_sim_16k : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 10, 2, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
CONSTANT c_tech_ddr3_sim_128k : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 10, 5, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
CONSTANT c_tech_ddr3_sim_1m : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 10, 8, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
CONSTANT c_tech_ddr3_sim_8k : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 10, 1, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
CONSTANT c_tech_ddr3_sim_16k : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 10, 2, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
CONSTANT c_tech_ddr3_sim_128k : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 10, 5, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
CONSTANT c_tech_ddr3_sim_1m : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 10, 8, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
CONSTANT c_tech_ddr3_16g_dual_rank_800m : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 16, 16, 11, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7);
CONSTANT c_tech_ddr3_4g_800m_master : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7);
CONSTANT c_tech_ddr3_4g_800m_slave : t_c_tech_ddr := ("DDR3", 800, FALSE, "DUAL ", 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7);
CONSTANT c_tech_ddr3_4g_single_rank_800m_master : t_c_tech_ddr := ("DDR3", 800, TRUE, "SINGLE", 16, 16, 10, 3, 64, 8, 8, 0, 0, 2, 1, 1, 0, 1, 14, 4, 2, 4, 64, 7);
CONSTANT c_tech_ddr3_4g_single_rank_800m_slave : t_c_tech_ddr := ("DDR3", 800, FALSE, "SINGLE", 16, 16, 10, 3, 64, 8, 8, 0, 0, 2, 1, 1, 0, 1, 14, 4, 2, 4, 64, 7);
CONSTANT c_tech_ddr3_16g_dual_rank_800m : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 16, 16, 11, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64);
CONSTANT c_tech_ddr3_4g_800m_master : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64);
CONSTANT c_tech_ddr3_4g_800m_slave : t_c_tech_ddr := ("DDR3", 800, FALSE, "DUAL ", 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64);
CONSTANT c_tech_ddr3_4g_single_rank_800m_master : t_c_tech_ddr := ("DDR3", 800, TRUE, "SINGLE", 16, 16, 10, 3, 64, 8, 8, 0, 0, 2, 1, 1, 0, 1, 14, 4, 2, 4, 64, 7, 64);
CONSTANT c_tech_ddr3_4g_single_rank_800m_slave : t_c_tech_ddr := ("DDR3", 800, FALSE, "SINGLE", 16, 16, 10, 3, 64, 8, 8, 0, 0, 2, 1, 1, 0, 1, 14, 4, 2, 4, 64, 7, 64);
--CONSTANT c_tech_ddr4_max : t_c_tech_ddr := ("none", 1600, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7); -- maximum ranges for record field definitions
CONSTANT c_tech_ddr4_max : t_c_tech_ddr := ("none", 1600, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 2, 2, 2, 1, 2, 0, 8, 3, 8, 64, 7); -- maximum ranges for record field definitions
--CONSTANT c_tech_ddr4_max : t_c_tech_ddr := ("none", 1600, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72); -- maximum ranges for record field definitions
CONSTANT c_tech_ddr4_max : t_c_tech_ddr := ("none", 1600, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 2, 2, 2, 1, 2, 0, 8, 3, 8, 64, 7, 72); -- maximum ranges for record field definitions
-- use predefined c_tech_ddr4_sim or derive it using func_tech_ddr_sim_size()
CONSTANT c_tech_ddr4_sim_4k : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 10, 1, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
CONSTANT c_tech_ddr4_sim_8k : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 10, 2, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
CONSTANT c_tech_ddr4_sim_16k : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 10, 3, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
CONSTANT c_tech_ddr4_sim_128k : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 10, 6, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
CONSTANT c_tech_ddr4_sim_1m : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 10, 9, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
CONSTANT c_tech_ddr4_sim_4k : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 10, 1, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
CONSTANT c_tech_ddr4_sim_8k : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 10, 2, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
CONSTANT c_tech_ddr4_sim_16k : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 10, 3, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
CONSTANT c_tech_ddr4_sim_128k : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 10, 6, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
CONSTANT c_tech_ddr4_sim_1m : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 10, 9, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
CONSTANT c_tech_ddr4_4g_1600m : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7);
CONSTANT c_tech_ddr4_8g_1600m : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 2, 2, 2, 1, 2, 0, 8, 3, 8, 64, 7);
CONSTANT c_tech_ddr4_16g_1600m_72 : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 17, 16, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 1, 1, 0, 8, 3, 8, 64, 7);
CONSTANT c_tech_ddr4_16g_1600m_64 : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 17, 16, 10, 2, 64, 8, 0, 8, 2, 1, 1, 1, 1, 1, 0, 8, 3, 8, 64, 7);
CONSTANT c_tech_ddr4_8g_1600m_64 : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 17, 15, 10, 2, 64, 8, 0, 8, 2, 2, 2, 2, 1, 2, 0, 8, 3, 8, 64, 7);
CONSTANT c_tech_ddr4_4g_2000m : t_c_tech_ddr := ("DDR4", 2000, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7);
CONSTANT c_tech_ddr4_8g_2400m : t_c_tech_ddr := ("DDR4", 2400, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 2, 2, 2, 1, 2, 0, 8, 3, 8, 64, 7);
CONSTANT c_tech_ddr4_4g_1600m : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72);
CONSTANT c_tech_ddr4_8g_1600m : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 2, 2, 2, 1, 2, 0, 8, 3, 8, 64, 7, 72);
CONSTANT c_tech_ddr4_8g_1600m_64 : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 17, 15, 10, 2, 64, 8, 0, 8, 2, 2, 2, 2, 1, 2, 0, 8, 3, 8, 64, 7, 64);
CONSTANT c_tech_ddr4_16g_1600m_72_64 : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 17, 16, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 1, 1, 0, 8, 3, 8, 64, 7, 64); -- 72b connection from IP, 64b to memory module (used for unb2c slot II with 64 bit modules)
CONSTANT c_tech_ddr4_16g_1600m_64 : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 17, 16, 10, 2, 64, 8, 0, 8, 2, 1, 1, 1, 1, 1, 0, 8, 3, 8, 64, 7, 64);
CONSTANT c_tech_ddr4_4g_2000m : t_c_tech_ddr := ("DDR4", 2000, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72);
CONSTANT c_tech_ddr4_8g_2400m : t_c_tech_ddr := ("DDR4", 2400, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 2, 2, 2, 1, 2, 0, 8, 3, 8, 64, 7, 72);
-- PHY in, inout and out signal records
TYPE t_tech_ddr3_phy_in IS RECORD -- DDR3 Description
......@@ -227,9 +231,14 @@ PACKAGE BODY tech_ddr_pkg IS
FUNCTION func_tech_ddr_ctlr_data_w(c_ddr : t_c_tech_ddr) RETURN NATURAL IS
BEGIN
RETURN c_ddr.dq_w*c_ddr.rsl; -- CTLR data
RETURN c_ddr.mem_dq_w*c_ddr.rsl; -- CTLR data
END;
FUNCTION func_tech_ddr_ctlr_ip_data_w(c_ddr : t_c_tech_ddr) RETURN NATURAL IS
BEGIN
RETURN c_ddr.dq_w*c_ddr.rsl; -- CTLR data
END;
FUNCTION func_tech_ddr_sim_size(c_ddr : t_c_tech_ddr; sim_ctrl_addr_w : NATURAL) RETURN t_c_tech_ddr IS
VARIABLE v_ddr : t_c_tech_ddr := c_ddr;
VARIABLE v_ctrl_addr_w : NATURAL;
......@@ -257,5 +266,23 @@ PACKAGE BODY tech_ddr_pkg IS
END IF;
END;
FUNCTION func_tech_ddr_rewire_64b_to_72b(c_ddr : t_c_tech_ddr; vec_64b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE vec_72b : STD_LOGIC_VECTOR(func_tech_ddr_ctlr_ip_data_w(c_ddr) - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
FOR w in 0 TO c_ddr.rsl - 1 LOOP
vec_72b( w * c_ddr.dq_w + c_ddr.mem_dq_w - 1 DOWNTO w * c_ddr.dq_w) := vec_64b((w+1) * c_ddr.mem_dq_w - 1 DOWNTO w * c_ddr.mem_dq_w);
END LOOP;
RETURN vec_72b;
END;
FUNCTION func_tech_ddr_rewire_72b_to_64b(c_ddr : t_c_tech_ddr; vec_72b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE vec_64b : STD_LOGIC_VECTOR(func_tech_ddr_ctlr_data_w(c_ddr) - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
FOR w in 0 TO c_ddr.rsl - 1 LOOP
vec_64b((w+1) * c_ddr.mem_dq_w - 1 DOWNTO w * c_ddr.mem_dq_w) := vec_72b( w * c_ddr.dq_w + c_ddr.mem_dq_w - 1 DOWNTO w * c_ddr.dq_w);
END LOOP;
RETURN vec_64b;
END;
END tech_ddr_pkg;
libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
+ 8
− 0
View file @ a2eaacec
......@@ -34,5 +34,13 @@ vmap altera_emif_cal_slave_nf_191 ./work/
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_cal_slave_nf_191_rmzieji.vhd" -work altera_emif_cal_slave_nf_191
#ddr4_16g_1600_64b
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_cal_slave_nf_191_rmzieji.vhd" -work altera_emif_cal_slave_nf_191
# ddr4_16g_1600_72b
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_cal_slave_nf_191_rmzieji.vhd" -work altera_emif_cal_slave_nf_191
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