The FIFO can handle continuous input data without gap.

libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd

@@ -45,8 +45,10 @@
 --   that is a power of 2, so g_fifo_size = true_log_pow2(largest block size +
 --   c_fifo_tx_fill_margin).
 -- Remark:
--- * The dp_fifo_fill_eop cannot handle continues stream of blocks without a
---   gap between blocks it needs 1 cycle to process a block.
+-- * The dp_fifo_fill_eop can handle continues stream of blocks without a
+--   gap between blocks, as shown by tb_dp_fifo_fill_eop.vhd, because
+--   snk_out.ready remains active and the FIFO does not run full. This was
+--   fixed by Reinier in Nov 2021 as part of L2SDP-505.
 --
 -------------------------------------------------------------------------------
 

libraries/base/ring/src/vhdl/ring_lane.vhd

@@ -21,16 +21,11 @@
 -------------------------------------------------------------------------------
 --
 -- Author: R. van der Walle
-
+--
 -- Purpose: Implement the function of a complete ring lane by combining ring_lane/tx.
--- Description: See https://support.astron.nl/confluence/x/jyu7Ag
+-- Description:
+-- . See "L5 SDPFW Design Document: Ring" at https://support.astron.nl/confluence/x/jyu7Ag
 -- Remark:
--- . Note that the dp_fifo_fill_eop in dp_block_validate_err cannot handle
---   continues stream of blocks without a gap between blocks the dp_fifo_fill_eop
---   needs 1 cycle to process a block. Streaming without gaps may cause the fifo
---   to overflow. Bursts of blocks can be handled by increasing gvalidate_err_fifo_size.
-
--------------------------------------------------------------------------------
 
 library IEEE, common_lib, mm_lib, dp_lib;
 use IEEE.std_logic_1164.all;