-Moved output stage from BG design to main design.

applications/arts/designs/arts_unb1_sc4/hdllib.cfg

 hdl_lib_name = arts_unb1_sc4
 hdl_library_clause_name = arts_unb1_sc4_lib
-hdl_lib_uses_synth = common dp mm diag bf tr_10GbE apertif unb1_board arts_unb1_sc4_bg
+hdl_lib_uses_synth = common dp mm diag bf tr_10GbE apertif unb1_board
 hdl_lib_uses_sim = apertif_unb1_fn_bf_emu
 hdl_lib_technology = ip_stratixiv
 
@@ -8,6 +8,14 @@ synth_files =
     ../../../apertif/designs/apertif_unb1_correlator/src/vhdl/node_apertif_unb1_correlator_mesh.vhd
     src/vhdl/arts_unb1_sc4_input.vhd
     src/vhdl/arts_unb1_sc4_processing.vhd
+    src/vhdl/arts_unb1_sc4_output_framer.vhd
+    src/vhdl/arts_unb1_sc4_output_iquv_reorder.vhd
+    src/vhdl/arts_unb1_sc4_output_iquv_framer.vhd
+    src/vhdl/arts_unb1_sc4_output_iquv_packetizer.vhd
+    src/vhdl/arts_unb1_sc4_output_i_reorder.vhd
+    src/vhdl/arts_unb1_sc4_output_i_framer.vhd
+    src/vhdl/arts_unb1_sc4_output_i_packetizer.vhd
+    src/vhdl/arts_unb1_sc4_output.vhd
     src/vhdl/arts_unb1_sc4_mm_master.vhd
     src/vhdl/arts_unb1_sc4.vhd
 

applications/arts/designs/arts_unb1_sc4_bg/hdllib.cfg

 hdl_lib_name = arts_unb1_sc4_bg
 hdl_library_clause_name = arts_unb1_sc4_bg_lib
-hdl_lib_uses_synth = common dp mm diag bf tr_10GbE apertif unb1_board 
+hdl_lib_uses_synth = common dp mm diag bf tr_10GbE apertif unb1_board arts_unb1_sc4_lib
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    src/vhdl/arts_unb1_sc4_output_framer.vhd
-    src/vhdl/arts_unb1_sc4_output_iquv_reorder.vhd
-    src/vhdl/arts_unb1_sc4_output_iquv_framer.vhd
-    src/vhdl/arts_unb1_sc4_output_iquv_packetizer.vhd
-    src/vhdl/arts_unb1_sc4_output_i_reorder.vhd
-    src/vhdl/arts_unb1_sc4_output_i_framer.vhd
-    src/vhdl/arts_unb1_sc4_output_i_packetizer.vhd
-    src/vhdl/arts_unb1_sc4_output.vhd
     src/vhdl/arts_unb1_sc4_bg_mm_master.vhd
 #    ../../../apertif/designs/apertif_unb1_correlator/src/vhdl/node_apertif_unb1_correlator_mesh.vhd
     src/vhdl/arts_unb1_sc4_bg.vhd

applications/arts/designs/arts_unb1_sc4_bg/src/vhdl/arts_unb1_sc4_bg.vhd

@@ -477,7 +477,8 @@ BEGIN
     g_mm_clk_freq             => c_unb1_board_mm_clk_freq_50M,
     g_dp_clk_use_xo_pll       => TRUE, -- Use internal PLL to generate dp_clk
     g_dp_clk_use_pll          => FALSE, 
-    g_xo_clk_use_pll          => TRUE -- Use internal PLL to generate mm_clk
+    g_xo_clk_use_pll          => TRUE, -- Use internal PLL to generate mm_clk,
+    g_pps_delay_max => 10000
   )
   PORT MAP (
     -- Clock and reset signals