Skip to content
Snippets Groups Projects
Commit a0000ab5 authored by Pieter Donker's avatar Pieter Donker
Browse files

Merge branch 'CWG-44' into 'master'

Resolve CWG-44

Closes CWG-44

See merge request desp/hdl!316
parents ec5bfcde 355429db
No related branches found
No related tags found
1 merge request!316Resolve CWG-44
Pipeline #46173 passed
......@@ -26,15 +26,93 @@
# . See https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+Gitlab+pipeline+automation+to+test+SDPFW+with+OPC+UA
stages:
- linting
- simulation
- synthesis
- hardware
lint-vhdl-lib-base:
tags:
- hdl
stage: linting
allow_failure: true
before_script:
- pip3 install vsg --use-pep517
script:
- cd libraries/base
- find . -name "*.vhd" -exec vsg -c ../../vsg_config.yaml -f {} \;
lint-vhdl-lib-dsp:
tags:
- hdl
stage: linting
allow_failure: true
before_script:
- pip3 install vsg --use-pep517
script:
- cd libraries/dsp
- find . -name "*.vhd" -exec vsg -c ../../vsg_config.yaml -f {} \;
lint-vhdl-lib-io:
tags:
- hdl
stage: linting
allow_failure: true
before_script:
- pip3 install vsg --use-pep517
script:
- cd libraries/io
- find . -name "*.vhd" -exec vsg -c ../../vsg_config.yaml -f {} \;
lint-vhdl-lib-technology:
tags:
- hdl
stage: linting
allow_failure: true
before_script:
- pip3 install vsg --use-pep517
script:
- cd libraries/technology
- find . -name "*.vhd" -exec vsg -c ../../vsg_config.yaml -f {} \;
lint-vhdl-boards-uniboard2b:
tags:
- hdl
stage: linting
allow_failure: true
before_script:
- pip3 install vsg --use-pep517
script:
- cd boards/uniboard2b
- find . -name "*.vhd" -exec vsg -c ../../vsg_config.yaml -f {} \;
lint-vhdl-boards-uniboard2c:
tags:
- hdl
stage: linting
allow_failure: true
before_script:
- pip3 install vsg --use-pep517
script:
- cd boards/uniboard2c
- find . -name "*.vhd" -exec vsg -c ../../vsg_config.yaml -f {} \;
lint-vhdl-applications-lofar2:
tags:
- hdl
stage: linting
allow_failure: true
before_script:
- pip3 install vsg --use-pep517
script:
- cd applications/lofar2
- find . -name "*.vhd" -exec vsg -c ../../vsg_config.yaml -f {} \;
###############################################################################
# HDL simulation stage
###############################################################################
sim-compile:
tags:
tags:
- fpga
stage: simulation
script:
......@@ -46,12 +124,12 @@ sim-compile:
- build/
sim-run:
tags:
tags:
- fpga
stage: simulation
script:
- echo "Running simulations"
# - test -f "build/info.txt" # This fails despite having artifact (see
# - test -f "build/info.txt" # This fails despite having artifact (see
# sim-compile code block where a folder and
# file are generated and preserved by using
# 'artifacts').
......@@ -60,21 +138,21 @@ sim-run:
# HDL synthesis stage
###############################################################################
synth-compile:
tags:
tags:
- fpga
stage: synthesis
script:
- echo "Compiling for synthesis"
synth-check-fmax:
tags:
tags:
- fpga
stage: synthesis
script:
- echo "Checking achieved fMax"
synth-check-programming-files:
tags:
tags:
- fpga
stage: synthesis
script:
......
# Gitlab CI/CD
HDL linting is using *gitlab-runners* on *dop349*.
Linting tool used is *vhdl-style-guide* (VSG)
link: https://vhdl-style-guide.readthedocs.io/en/latest/index.html
##### Linting settings.
By default all rules are disabled in de *vsg_config.yaml* file.
The only active rule on this moment is *case.keyword* and is set to *upper*.
rule:
global:
disable: True
group:
case::keyword:
disable: False
case: 'upper'
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment