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Commit 9fc24b8b authored by Zanting's avatar Zanting
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Moved rtl and stratixiv ip from UNB to RadioHDL

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......@@ -31,11 +31,6 @@ USE common_lib.common_pkg.ALL;
-- and the independent products in the product vector will be:
-- p = a(1)*b(1) & a(0)*b(0)
--
-- Architectures:
-- . rtl : uses RTL to have all registers in one clocked process
-- . stratix4 : uses LPM_MULT component directly, similar as MegaWizard does
-- as becomes clear from dsp_mult.vhd
--
-- Remarks:
-- . When g_out_p_w < g_in_a_w+g_in_b_w then the common_mult truncates the
-- MSbit of the product.
......@@ -43,12 +38,11 @@ USE common_lib.common_pkg.ALL;
-- g_out_p_w = c_prod_w-1 to skip the double sign bit that is only needed
-- when the maximum positive product -2**(g_in_a_w-1) * -2**(g_in_b_w-1) has
-- to be represented, which is typically not needed in DSP.
--
-- Preferred architecture: 'stratix4', see synth\quartus\common_top.vhd
ENTITY common_mult IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_variant : STRING := "IP";
g_in_a_w : POSITIVE := 18;
g_in_b_w : POSITIVE := 18;
g_out_p_w : POSITIVE := 36; -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
......@@ -67,3 +61,55 @@ ENTITY common_mult IS
out_p : OUT STD_LOGIC_VECTOR(g_nof_mult*g_out_p_w-1 DOWNTO 0)
);
END common_mult;
ARCHITECTURE str OF common_mult IS
-- Extra output pipelining using common_pipeline is only needed when g_pipeline_output > 1
CONSTANT c_pipeline_output : NATURAL := sel_a_b(g_pipeline_output>0, g_pipeline_output-1, 0);
SIGNAL result : STD_LOGIC_VECTOR(out_p'RANGE); -- stage dependent on g_pipeline_output being 0 or 1
BEGIN
u_mult : ENTITY tech_mult_lib.tech_mult
GENERIC MAP(
g_technology => g_technology,
g_variant => g_variant,
g_in_a_w => g_in_a_w,
g_in_b_w => g_in_b_w,
g_out_p_w => g_out_p_w,
g_nof_mult => g_nof_mult,
g_pipeline_input => g_pipeline_input,
g_pipeline_product => g_pipeline_product,
g_pipeline_output => g_pipeline_output,
g_representation => g_representation
)
PORT MAP(
rst => rst,
clk => clk,
clken => clken,
in_a => in_a,
in_b => in_b,
out_p => result
);
------------------------------------------------------------------------------
-- Extra output pipelining
------------------------------------------------------------------------------
u_output_pipe : ENTITY common_lib.common_pipeline -- pipeline output
GENERIC MAP (
g_representation => g_representation,
g_pipeline => c_pipeline_output,
g_in_dat_w => result'LENGTH,
g_out_dat_w => result'LENGTH
)
PORT MAP (
rst => rst,
clk => clk,
clken => clken,
in_dat => STD_LOGIC_VECTOR(result),
out_dat => out_p
);
END str;
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