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Commit 9f3ddd8a authored by Reinier van der Walle's avatar Reinier van der Walle
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###############################################################################
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, unb2b_test_lib;
USE IEEE.std_logic_1164.ALL;
ENTITY tb_unb2b_test_10GbE IS
END tb_unb2b_test_10GbE;
ARCHITECTURE tb OF tb_unb2b_test_10GbE IS
BEGIN
u_tb_unb2b_test : ENTITY unb2b_test_lib.tb_unb2b_test
GENERIC MAP (
g_design_name => "unb2b_test_10GbE"
);
END tb;
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_test_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE unb2b_board_lib.unb2_board_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
ENTITY unb2b_test_10GbE IS
GENERIC (
g_design_name : STRING := "unb2b_test_10GbE";
g_design_note : STRING := "10GbE: all QSFPs";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
);
PORT (
-- GENERAL
CLK : IN STD_LOGIC; -- System Clock
PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
SENS_SC : INOUT STD_LOGIC;
SENS_SD : INOUT STD_LOGIC;
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
-- Transceiver clocks
SA_CLK : IN STD_LOGIC; -- Clock 10GbE front (qsfp) and ring lines
SB_CLK : IN STD_LOGIC; -- Clock 10GbE back upper 24 lines
BCK_REF_CLK : IN STD_LOGIC; -- Clock 10GbE back lower 24 lines
-- back transceivers
-- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
-- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
-- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
-- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
-- ring transceivers
-- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : INOUT STD_LOGIC;
PMBUS_SD : INOUT STD_LOGIC;
PMBUS_ALERT : IN STD_LOGIC;
-- front transceivers
QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
);
END unb2b_test_10GbE;
ARCHITECTURE str OF unb2b_test_10GbE IS
BEGIN
u_revision : ENTITY unb2b_test_lib.unb2b_test
GENERIC MAP (
g_design_name => g_design_name,
g_design_note => g_design_note,
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn
)
PORT MAP (
-- GENERAL
CLK => CLK,
PPS => PPS,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- Others
VERSION => VERSION,
ID => ID,
TESTIO => TESTIO,
-- I2C Interface to Sensors
SENS_SC => SENS_SC,
SENS_SD => SENS_SD,
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT,
-- Transceiver clocks
SA_CLK => SA_CLK,
SB_CLK => SB_CLK,
BCK_REF_CLK => BCK_REF_CLK,
-- back transceivers
-- BCK_RX => BCK_RX,
-- BCK_TX => BCK_TX,
BCK_SDA => BCK_SDA,
BCK_SCL => BCK_SCL,
BCK_ERR => BCK_ERR,
-- ring transceivers
-- RING_0_RX => RING_0_RX,
-- RING_0_TX => RING_0_TX,
-- RING_1_RX => RING_1_RX,
-- RING_1_TX => RING_1_TX,
-- pmbus
PMBUS_SC => PMBUS_SC,
PMBUS_SD => PMBUS_SD,
PMBUS_ALERT => PMBUS_ALERT,
-- front transceivers
QSFP_0_RX => QSFP_0_RX,
QSFP_0_TX => QSFP_0_TX,
QSFP_1_RX => QSFP_1_RX,
QSFP_1_TX => QSFP_1_TX,
QSFP_2_RX => QSFP_2_RX,
QSFP_2_TX => QSFP_2_TX,
QSFP_3_RX => QSFP_3_RX,
QSFP_3_TX => QSFP_3_TX,
QSFP_4_RX => QSFP_4_RX,
QSFP_4_TX => QSFP_4_TX,
QSFP_5_RX => QSFP_5_RX,
QSFP_5_TX => QSFP_5_TX,
QSFP_SDA => QSFP_SDA,
QSFP_SCL => QSFP_SCL,
QSFP_LED => QSFP_LED
);
END str;
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