initial commit

boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl

+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+

boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/README.txt

+
+
+Simulation
+----------
+-> Read ../../doc/README first until step 3
+Modelsim instructions:
+
+    # in Modelsim do:
+    lp unb2b_test_10GbE
+    mk all
+    # now double click on testbench file
+    as 10
+    run 500us
+
+
+    # while the simulation runs... in another terminal/bash session do:
+    cd unb2b_test/tb/python
+
+    # To read out the design_name, ppsh and sensors; do:
+    python tc_unb2b_test.py --sim --unb 0 --fn 3 --seq INFO,PPSH,SENSORS 
+    # (sensor results only show up after 1000us of simulation runtime)
+
+    # To test the 10GbE offload; do:
+    python tc_unb2b_test.py --sim --unb 0 --fn 3 --seq BGDB -s 10GBE -r 0
+
+
+    # to end simulation in Modelsim do:
+    quit -sim
+
+
+
+Testing on hardware
+-------------------
+-> Read ../../doc/README first until step 5
+
+# (assume that the Uniboard is --unb 1)
+
+# To read out the design_name, ppsh and sensors; do:
+
+python tc_unb2b_test.py --unb 1 --fn 0:3 --seq REGMAP,INFO,PPSH,SENSORS -v5
+
+# To test the 10GbE offload:
+
+python tc_unb2b_test.py --unb 1 --fn 0:3 --seq REGMAP,BGDB -v5 -s 10GBE -r 0:15 -v 3 --rep -1
+
+

boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg

+hdl_lib_name = unb2b_test_10GbE
+hdl_library_clause_name = unb2b_test_10GbE_lib
+hdl_lib_uses_synth = common mm technology unb2b_board unb2b_test
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+hdl_lib_include_ip = 
+                     # Comment all IP that is not used in this design
+                     # 10GbE
+                     ip_arria10_e1sg_mac_10g
+                     ip_arria10_e1sg_pll_xgmii_mac_clocks
+                     ip_arria10_e1sg_transceiver_pll_10g
+                     
+                     ip_arria10_e1sg_phy_10gbase_r
+                     ip_arria10_e1sg_phy_10gbase_r_4
+                     ip_arria10_e1sg_phy_10gbase_r_12
+                     ip_arria10_e1sg_phy_10gbase_r_24
+                     ip_arria10_e1sg_phy_10gbase_r_48
+                     
+                     ip_arria10_e1sg_transceiver_reset_controller_1
+                     ip_arria10_e1sg_transceiver_reset_controller_4
+                     ip_arria10_e1sg_transceiver_reset_controller_12
+                     ip_arria10_e1sg_transceiver_reset_controller_24
+                     ip_arria10_e1sg_transceiver_reset_controller_48
+
+synth_files =
+    unb2b_test_10GbE.vhd
+
+test_bench_files = 
+    tb_unb2b_test_10GbE.vhd
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+    ../../src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+     ../../quartus .
+#    ../../quartus/qsys_unb2b_test.qsys .
+#    ../../quartus/quartus.ini .
+#    ../../quartus/pm_uc_ES1_ww05p1.hex .
+    ../../src/hex hex
+
+quartus_qsf_files =
+    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+quartus_sdc_pre_files =
+    quartus/unb2b_test_10GbE.sdc
+    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board_pre.sdc
+
+quartus_sdc_files =
+    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+    quartus/unb2b_test_10GbE_pins.tcl
+
+quartus_vhdl_files = 
+
+quartus_qip_files =
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_10GbE/qsys_unb2b_test/synthesis/qsys_unb2b_test.qip

boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE.sdc

+#set_false_path -from [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}] -to [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]