Initial commit

boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb1_board_lib, technology_lib, tech_ddr_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+
+ENTITY tb_unb1_ddr3_reorder_dual_rank IS
+    GENERIC (
+      g_design_name : STRING       := "unb1_ddr3_reorder_dual_rank";     
+      g_design_note : STRING       := "Reference Reorder";  
+      g_sim_unb_nr  : NATURAL      := 0; -- UniBoard 0
+      g_sim_node_nr : NATURAL      := 7; -- Back node 3
+      g_tech_ddr    : t_c_tech_ddr := c_tech_ddr3_4g_800m_master
+    );
+END tb_unb1_ddr3_reorder_dual_rank;
+
+ARCHITECTURE tb OF tb_unb1_ddr3_reorder_dual_rank IS
+
+BEGIN
+  u_tb_revision : ENTITY work.tb_unb1_ddr3_reorder
+    GENERIC MAP(
+      g_design_name => g_design_name,
+      g_design_note => g_design_note,
+      g_sim_unb_nr  => g_sim_unb_nr, 
+      g_sim_node_nr => g_sim_node_nr,
+      g_tech_ddr    => g_tech_ddr   
+  );
+  
+END tb;

boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, technology_lib, tech_ddr_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+
+ENTITY unb1_ddr3_reorder_dual_rank IS
+  GENERIC (
+    g_design_name : STRING       := "unb1_ddr3_reorder_dual_rank"; -- use revision name = entity name = design name
+    g_design_note : STRING       := "Reference Reorder";
+    g_sim         : BOOLEAN      := FALSE; 
+    g_sim_unb_nr  : NATURAL      := 0;
+    g_sim_node_nr : NATURAL      := 4;
+    -- Stamps are passed via QIP at compile start if $UNB_COMPILE_STAMPS is set
+    g_stamp_date  : NATURAL      := 0;     -- Date (YYYYMMDD)
+    g_stamp_time  : NATURAL      := 0;     -- Time (HHMMSS)
+    g_stamp_svn   : NATURAL      := 0;     -- SVN revision
+    g_use_MB_I    : NATURAL      := 1;              -- 1: use MB_I  0: do not use
+    g_tech_ddr    : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
+    g_aux         : t_c_unb1_board_aux := c_unb1_board_aux
+  );
+  PORT (
+    -- GENERAL
+    CLK           : IN    STD_LOGIC; -- System Clock 
+    PPS           : IN    STD_LOGIC; -- System Sync
+    WDI           : OUT   STD_LOGIC; -- Watchdog Clear   
+    INTA          : INOUT STD_LOGIC; -- FPGA interconnect line
+    INTB          : INOUT STD_LOGIC; -- FPGA interconnect line
+
+    -- Others
+    VERSION       : IN    STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+    ID            : IN    STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+    TESTIO        : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+    -- I2C Interface to Sensors
+    sens_sc       : INOUT STD_LOGIC;
+    sens_sd       : INOUT STD_LOGIC;
+
+    -- 1GbE Control Interface
+    ETH_clk       : IN    STD_LOGIC;
+    ETH_SGIN      : IN    STD_LOGIC;
+    ETH_SGOUT     : OUT   STD_LOGIC;
+
+    -- SO-DIMM Memory Bank I
+    MB_I_IN       : IN    t_tech_ddr3_phy_in;
+    MB_I_IO       : INOUT t_tech_ddr3_phy_io;
+    MB_I_OU       : OUT   t_tech_ddr3_phy_ou
+  );
+END unb1_ddr3_reorder_dual_rank;
+
+
+ARCHITECTURE str OF unb1_ddr3_reorder_dual_rank IS
+
+BEGIN
+  u_revision : ENTITY work.unb1_ddr3_reorder
+  GENERIC MAP(
+    g_design_name => g_design_name,
+    g_design_note => g_design_note,
+    g_sim         => g_sim,         
+    g_sim_unb_nr  => g_sim_unb_nr,  
+    g_sim_node_nr => g_sim_node_nr, 
+    g_stamp_date  => g_stamp_date,  
+    g_stamp_time  => g_stamp_time,  
+    g_stamp_svn   => g_stamp_svn,   
+    g_use_MB_I    => g_use_MB_I,    
+    g_tech_ddr    => g_tech_ddr,    
+    g_aux         => g_aux         
+  )
+  PORT MAP(
+    CLK       => CLK,           
+    PPS       => PPS,          
+    WDI       => WDI,          
+    INTA      => INTA,         
+    INTB      => INTB,         
+    VERSION   => VERSION,      
+    ID        => ID,           
+    TESTIO    => TESTIO, 
+    sens_sc   => sens_sc,      
+    sens_sd   => sens_sd,      
+    ETH_clk   => ETH_clk,      
+    ETH_SGIN  => ETH_SGIN,     
+    ETH_SGOUT => ETH_SGOUT,    
+    MB_I_IN   => MB_I_IN,      
+    MB_I_IO   => MB_I_IO,      
+    MB_I_OU   => MB_I_OU      
+  );    
+  
+END str;
+
+
+
+