Merge branch 'L2SDP-187' into 'master'

Resolve L2SDP-187

Closes L2SDP-187

See merge request desp/hdl!63

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/opencl_bsp_ip.qsf → applications/ta2/bsp/hardware/ta2_unb2b_bsp/opencl_bsp_ip.qsf

@@ -24,12 +24,12 @@ source device.tcl
 #============================================================
 set_global_assignment -name TOP_LEVEL_ENTITY top
 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
-set_global_assignment -name VHDL_FILE top_components_pkg.vhd
-set_global_assignment -name VHDL_FILE top.vhd
-set_global_assignment -name VERILOG_FILE ip/freeze_wrapper.v
-set_global_assignment -name VERILOG_FILE ip/pr_region.v
+#set_global_assignment -name VHDL_FILE top_components_pkg.vhd
+#set_global_assignment -name VHDL_FILE top.vhd
+#set_global_assignment -name VERILOG_FILE ip/freeze_wrapper.v
+#set_global_assignment -name VERILOG_FILE ip/pr_region.v
 set_global_assignment -name QIP_FILE ip/kernel_mem/kernel_mem_mm_bridge_0/kernel_mem_mm_bridge_0.qip
-set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Pro Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "19.2.0 Pro Edition"
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
 set_global_assignment -name DEVICE 10AX115U2F45E1SG
@@ -38,13 +38,9 @@ set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1932
 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 4
 
-set_global_assignment -name QSYS_FILE board.qsys
+set_global_assignment -name SOURCE_TCL_SCRIPT_FILE radiohdl_components.qsf
 
-set_global_assignment -name VHDL_FILE ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
-set_global_assignment -name VHDL_FILE ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
-set_global_assignment -name VHDL_FILE ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd
-set_global_assignment -name VHDL_FILE ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
-set_global_assignment -name VHDL_FILE ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
+set_global_assignment -name QSYS_FILE board.qsys
 
 set_global_assignment -name IP_FILE ip/board/board_reg_unb_pmbus.ip
 set_global_assignment -name IP_FILE ip/board/board_kernel_clk_gen.ip

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/scripts/post_flow_pr.tcl → applications/ta2/bsp/hardware/ta2_unb2b_bsp/scripts/post_flow_pr.tcl

@@ -14,7 +14,32 @@
 # sole purpose of programming logic devices manufactured by Intel and sold by    
 # Intel or its authorized distributors.  Please refer to the applicable          
 # agreement for further details.                                                 
+# ##########################################################################
+# Copyright 2020
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# ##########################################################################
 
+# ##########################################################################
+# Author:
+# . Reinier vd Walle 
+# Purpose:
+# . post-compile script for OpenCL applications
+# Description:
+# . " "
+# ##########################################################################
 post_message "Running post_flow_pr.tcl script"
 
 post_message "Checking for OpenCL SDK installation, environment should have INTELFPGAOCLSDKROOT defined"

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/scripts/pre_flow_pr.tcl → applications/ta2/bsp/hardware/ta2_unb2b_bsp/scripts/pre_flow_pr.tcl

@@ -14,7 +14,32 @@
 # sole purpose of programming logic devices manufactured by Intel and sold by    
 # Intel or its authorized distributors.  Please refer to the applicable          
 # agreement for further details.                                                 
+# ##########################################################################
+# Copyright 2020
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# ##########################################################################
 
+# ##########################################################################
+# Author:
+# . Reinier vd Walle
+# Purpose:
+# . pre-compile script for OpenCL applications
+# Description:
+# . " "
+# ##########################################################################
 post_message "Running pre-flow script"
 
 # Make sure OpenCL SDK installation exists
@@ -42,19 +67,20 @@ if {[catch {set radiohdl_build $::env(RADIOHDL_BUILD_DIR)} result]} {
 source "$sdk_root/ip/board/bsp/opencl_bsp_util.tcl"
 
 set project_name  top
-set revision_name UNKNOWN
+set revision_name flat
+set board_name UNKNOWN
 
-# Get revision name (from quartus(args) variable)
+# Get board name (from quartus(args) variable)
 if { [llength $quartus(args)] > 0 } {
-  set revision_name [lindex $quartus(args) 0]
+  set board_name [lindex $quartus(args) 0]
 } else {
-  set revision_name top
+  set board_name ta2_unb2b_bsp
 }
 
 set fast_compile  [::aocl_fast_compile::is_fast_compile]
 set device_name   [::opencl_bsp::get_device_name $project_name $revision_name]
 
-
+# Make sure 
 ##############################################################################
 ##############################       MAIN        #############################
 ##############################################################################
@@ -72,6 +98,26 @@ if {$revision_name eq "flat"} {
   exit 2
 }  
  
+# Copy qsf file
+if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf"] == 1} {
+  file copy -force $::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf radiohdl_components.qsf 
+} else {
+  post_message -type error "It seems that the BSP has not been initialized yet, please execute the following commands and try again:"
+  post_message -type error "quartus_config unb2b; run_qsys unb2b $board_name board.qsys"
+  post_message -type error "Terminating pre-flow script"
+  exit 2
+
+}
+# Copy memory initialization file
+if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex"] == 1} {
+  file copy -force $::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex onchip_memory2_0.hex 
+} else {
+  post_message -type error "It seems that the BSP has not been initialized yet, please execute the following commands and try again:"
+  post_message -type error "quartus_config unb2b; run_qsys unb2b $board_name board.qsys"
+  post_message -type error "Terminating pre-flow script"
+  exit 2
+
+}
 
 post_message "Compiling $revision_name revision: generating and archiving board.qsys"
 post_message "    qsys-generate -syn --family=\"Arria 10\" --part=$device_name board.qsys"

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top.vhd → applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd

--------------------------------------------------------------------------------
---
--- Copyright (C) 2020
+-- --------------------------------------------------------------------------
+-- Copyright 2020
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- http://www.apache.org/licenses/LICENSE-2.0
 --
--------------------------------------------------------------------------------
-
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, tech_ddr_lib;
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+
+-- --------------------------------------------------------------------------
+-- Author:
+-- . Reinier vd Walle
+-- Purpose:
+-- . Top-Level for OpenCL Board Support Package of TA2 applications
+-- Description:
+-- . This BSP makes several IO-channels available to the OpenCL kernel, these
+--   include:
+--   . 40 GbE
+--   . 10 GbE
+--   . ADC
+--   . 1 GbE M&C
+-- --------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, tech_ddr_lib, ta2_unb2b_40GbE_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_1gbe_mc_lib, ta2_unb2b_mm_io_lib, ta2_unb2b_jesd204b_lib ;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
@@ -435,7 +445,7 @@ BEGIN
   unb2b_board_ring_io_serial_tx_arr(3+c_ring_bus_w DOWNTO c_ring_bus_w) <= ta2_unb2b_40GbE_tx_serial_r(11 DOWNTO 8);
   ta2_unb2b_40GbE_rx_serial_r(11 DOWNTO 8) <= unb2b_board_ring_io_serial_rx_arr(3+c_ring_bus_w DOWNTO c_ring_bus_w);
 
-  u_ta2_unb2b_40GbE : ENTITY work.ta2_unb2b_40GbE
+  u_ta2_unb2b_40GbE : ENTITY ta2_unb2b_40GbE_lib.ta2_unb2b_40GbE
   GENERIC MAP (
     g_nof_mac => c_nof_40GbE_IP
   )
@@ -465,7 +475,7 @@ BEGIN
   ta2_unb2b_10GbE_rx_serial_r(0) <= unb2b_board_front_io_serial_rx_arr(0);
 
 
-  u_ta2_unb2b_10GbE : ENTITY work.ta2_unb2b_10GbE
+  u_ta2_unb2b_10GbE : ENTITY ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
   GENERIC MAP (
     g_nof_mac => c_nof_10GbE_IP
   )
@@ -491,7 +501,7 @@ BEGIN
   -----------------------------
   -- 1GbE Monitoring & Control
   -----------------------------
-  u_ta2_unb2b_1GbE_mc : ENTITY work.ta2_unb2b_1GbE_mc
+  u_ta2_unb2b_1GbE_mc : ENTITY ta2_unb2b_1GbE_mc_lib.ta2_unb2b_1GbE_mc
   PORT MAP (
     st_clk           => st_clk,
     st_rst           => st_rst,
@@ -514,7 +524,7 @@ BEGIN
   -----------------------------
   -- Monitoring & Control UNB protocol
   -----------------------------
-  u_ta2_unb2b_mm_io : ENTITY work.ta2_unb2b_mm_io
+  u_ta2_unb2b_mm_io : ENTITY ta2_unb2b_mm_io_lib.ta2_unb2b_mm_io
   PORT MAP (
     mm_clk        =>  mm_clk,         
     mm_rst        =>  mm_rst,
@@ -539,7 +549,7 @@ BEGIN
   ----------
   -- ADC
   ----------
-  u_ta2_unb2b_jesd204b : ENTITY work.ta2_unb2b_jesd204b
+  u_ta2_unb2b_jesd204b : ENTITY ta2_unb2b_jesd204b_lib.ta2_unb2b_jesd204b
   GENERIC MAP(
     g_nof_streams => c_nof_ADC
   )
@@ -564,9 +574,9 @@ BEGIN
     src_in_arr            => ta2_unb2b_ADC_src_in_arr   
   );
 
---  ----------
---  -- DDR4
---  ----------
+  ----------
+  -- DDR4
+  ----------
   --u_ta2_unb2b_ddr : ENTITY work.ta2_unb2b_ddr
   --GENERIC MAP(
   --  g_use_MB_II => FALSE
@@ -574,7 +584,7 @@ BEGIN
   --PORT MAP(      
   --  kernel_clk            => board_kernel_clk_clk, 
   --  kernel_reset          => i_kernel_rst, 
--- 
+ 
   --  mem0_waitrequest      => board_kernel_mem0_waitrequest, 
   --  mem0_readdata         => board_kernel_mem0_readdata, 
   --  mem0_readdatavalid    => board_kernel_mem0_readdatavalid, 
@@ -585,10 +595,10 @@ BEGIN
   --  mem0_read             => board_kernel_mem0_read, 
   --  mem0_byteenable       => board_kernel_mem0_byteenable, 
   --  mem0_debugaccess      => board_kernel_mem0_debugaccess, 
---
+
   --  mb_I_ref_clk          => MB_I_REF_CLK, 
   --  mb_I_ref_rst          => mb_I_ref_rst,   
---
+
   --  mb_I_in               => MB_I_IN, 
   --  mb_I_io               => MB_I_IO, 
   --  mb_I_ou               => MB_I_OU 
@@ -614,27 +624,27 @@ BEGIN
     board_kernel_cra_byteenable                 => board_kernel_cra_byteenable,
     board_kernel_cra_debugaccess                => board_kernel_cra_debugaccess,
 
-    board_kernel_mem0_waitrequest               => '0',         
-    board_kernel_mem0_readdata                  => c_ones,      
-    board_kernel_mem0_readdatavalid             => '1', 
-    board_kernel_mem0_burstcount                => OPEN,   
-    board_kernel_mem0_writedata                 => OPEN,   
-    board_kernel_mem0_address                   => OPEN,   
-    board_kernel_mem0_write                     => OPEN,   
-    board_kernel_mem0_read                      => OPEN,   
-    board_kernel_mem0_byteenable                => OPEN,   
-    board_kernel_mem0_debugaccess               => OPEN,
- 
---    board_kernel_mem0_waitrequest               => board_kernel_mem0_waitrequest,         
---    board_kernel_mem0_readdata                  => board_kernel_mem0_readdata,      
---    board_kernel_mem0_readdatavalid             => board_kernel_mem0_readdatavalid, 
---    board_kernel_mem0_burstcount                => board_kernel_mem0_burstcount,    
---    board_kernel_mem0_writedata                 => board_kernel_mem0_writedata,     
---    board_kernel_mem0_address                   => board_kernel_mem0_address,       
---    board_kernel_mem0_write                     => board_kernel_mem0_write,         
---    board_kernel_mem0_read                      => board_kernel_mem0_read,          
---    board_kernel_mem0_byteenable                => board_kernel_mem0_byteenable,    
---    board_kernel_mem0_debugaccess               => board_kernel_mem0_debugaccess,   
+    --board_kernel_mem0_waitrequest               => '0',         
+    --board_kernel_mem0_readdata                  => c_ones,      
+    --board_kernel_mem0_readdatavalid             => '1', 
+    --board_kernel_mem0_burstcount                => OPEN,   
+    --board_kernel_mem0_writedata                 => OPEN,   
+    --board_kernel_mem0_address                   => OPEN,   
+    --board_kernel_mem0_write                     => OPEN,   
+    --board_kernel_mem0_read                      => OPEN,   
+    --board_kernel_mem0_byteenable                => OPEN,   
+    --board_kernel_mem0_debugaccess               => OPEN,
+ 
+    board_kernel_mem0_waitrequest               => board_kernel_mem0_waitrequest,         
+    board_kernel_mem0_readdata                  => board_kernel_mem0_readdata,      
+    board_kernel_mem0_readdatavalid             => board_kernel_mem0_readdatavalid, 
+    board_kernel_mem0_burstcount                => board_kernel_mem0_burstcount,    
+    board_kernel_mem0_writedata                 => board_kernel_mem0_writedata,     
+    board_kernel_mem0_address                   => board_kernel_mem0_address,       
+    board_kernel_mem0_write                     => board_kernel_mem0_write,         
+    board_kernel_mem0_read                      => board_kernel_mem0_read,          
+    board_kernel_mem0_byteenable                => board_kernel_mem0_byteenable,    
+    board_kernel_mem0_debugaccess               => board_kernel_mem0_debugaccess,   
 
     board_kernel_register_mem_address           => board_kernel_register_mem_address,
     board_kernel_register_mem_clken             => board_kernel_register_mem_clken, 
@@ -811,6 +821,10 @@ BEGIN
     udp_rx_sosi_arr          =>  eth1g_udp_rx_sosi_arr,
     udp_rx_siso_arr          =>  eth1g_udp_rx_siso_arr,
  
+    -- RAM scrap
+    ram_scrap_mosi           => c_mem_mosi_rst,
+    ram_scrap_miso           => OPEN,        
+
     -- FPGA pins
     -- . General
     CLK                      => CLK,

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top_components_pkg.vhd → applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd

--------------------------------------------------------------------------------
---
--- Copyright (C) 2020
+-- --------------------------------------------------------------------------
+-- Copyright 2020
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- http://www.apache.org/licenses/LICENSE-2.0
 --
--------------------------------------------------------------------------------
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
 
+-- --------------------------------------------------------------------------
+-- Author:
+-- . Reinier vd Walle
+-- Purpose:
+-- . VHDL package for top.vhd
+-- Description:
+-- . Contains components instantiated by top.vhd
+-- --------------------------------------------------------------------------
 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;