Added fpga.yaml for FPGA design lofar2_unb2b_adc.

applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml

+schema_name   : args
+schema_version: 1.0
+schema_type   : fpga
+
+hdl_library_name: lofar2_unb2b_adc
+fpga_name       : lofar2_unb2b_adc
+fpga_description: "FPGA design lofar2_unb2b_adc"
+
+peripherals:
+  #############################################################################
+  # Factory
+  #############################################################################
+  - peripheral_name: unb2b_board/system_info
+    slave_port_names:
+      - ROM_SYSTEM_INFO
+      - PIO_SYSTEM_INFO
+    lock_base_address: 0x10000
+
+  - peripheral_name: unb2b_board/wdi
+    slave_port_names:
+      - PIO_WDI
+
+  - peripheral_name: unb2b_board/unb2_fpga_sens
+    slave_port_names:
+      - REG_FPGA_TEMP_SENS
+      - REG_FPGA_VOLTAGE_SENS
+    
+  - peripheral_name: unb2b_board/ram_scrap
+    slave_port_names:
+      - RAM_SCRAP
+      
+  - peripheral_name: eth/eth
+    slave_port_names:
+      - AVS_ETH_0_TSE
+      - AVS_ETH_0_REG
+      - AVS_ETH_0_RAM
+      
+  - peripheral_name: ppsh/ppsh
+    slave_port_names:
+      - PIO_PPS
+      
+  - peripheral_name: epcs/epcs
+    slave_port_names:
+      - REG_EPCS
+      
+  - peripheral_name: dp/dpmm
+    slave_port_names:
+      - REG_DPMM_CTRL
+      - REG_DPMM_DATA
+      
+  - peripheral_name: dp/mmdp
+    slave_port_names:
+      - REG_MMDP_CTRL
+      - REG_MMDP_DATA
+      
+  - peripheral_name: remu/remu
+    slave_port_names:
+      - REG_REMU
+ 
+  #############################################################################
+  # Application
+  #############################################################################
+  
+  - peripheral_name: tech_jesd204b/jesd_ctrl
+    slave_port_names:
+      - PIO_JESD_CTRL
+      
+  - peripheral_name: tech_jesd204b/jesd204b_arria10
+    slave_port_names:
+      - JESD204B
+  
+  - peripheral_name: dp/dp_shiftram
+    parameter_overrides:
+      - { name: g_nof_streams, value: 12 }  # = S_pn
+      - { name: g_nof_words, value: 4096 }
+      - { name: g_data_w, value: 16 }
+    slave_port_names:
+      - REG_DP_SHIFTRAM
+
+  - peripheral_name: dp/dp_bsn_source
+    parameter_overrides:
+      - { name: g_nof_block_per_sync, value: 195313 }  # 390625 = 2 * 195312, to have integer number of blocks in 2 s sync interval
+    slave_port_names:
+      - REG_BSN_SOURCE
+
+#  - peripheral_name: dp/dp_bsn_source_v2
+#    parameter_overrides:
+#      - { name: g_nof_clk_per_sync, value: 200000000 }  # = f_adc
+#      - { name: g_block_size, value: 1024 }       # = N_fft
+#      - { name: g_bsn_time_offset_w, value: 10 }  # note: g_bsn_time_offset_w = ceil_log2(g_block_size)
+#    slave_port_names:
+#      - REG_BSN_SOURCE_V2
+      
+  - peripheral_name: dp/dp_bsn_scheduler
+    slave_port_names:
+      - REG_BSN_SCHEDULER
+  
+  - peripheral_name: dp/dp_bsn_monitor
+    peripheral_group: input
+    slave_port_names:
+      - REG_BSN_MONITOR_INPUT
+  
+  - peripheral_name: diag/diag_wg_wideband
+    parameter_overrides:
+      - { name: g_nof_streams, value: 12 }  # = S_pn
+    slave_port_names:
+      - REG_DIAG_WG
+      - RAM_DIAG_WG
+      
+#  - peripheral_name: aduh/aduh_monitor
+#    slave_port_names:
+#      - REG_ADUH_MONITOR
+#      - RAM_ADUH_MONITOR
+
+  - peripheral_name: diag/diag_data_buffer
+    peripheral_group: bsn
+    parameter_overrides:
+      - { name: g_nof_streams, value: 12 }  # = S_pn
+      - { name: g_data_w, value: 16 }
+      - { name: g_nof_data, value: 1024 }
+    slave_port_names:
+      - REG_DIAG_DATA_BUF_BSN
+      - RAM_DIAG_DATA_BUF_BSN
+