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Commit 9e2d3015 authored by Reinier van der Walle's avatar Reinier van der Walle
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Merge branch 'L2SDP-832' into 'master' 

Resolve L2SDP-832

Closes L2SDP-832

See merge request desp/hdl!284
parents 57171a38 bbf5a219
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1 merge request!284Resolve L2SDP-832
Pipeline #37366 passed
Stage: simulation
Stage: synthesis
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applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
+ 29
− 3
View file @ 9e2d3015
...@@ -39,9 +39,35 @@ number_of_columns = 13 ...@@ -39,9 +39,35 @@ number_of_columns = 13
REG_FPGA_TEMP_SENS 1 1 REG temp 0x00018000 1 RO uint32 b[31:0] - - - REG_FPGA_TEMP_SENS 1 1 REG temp 0x00018000 1 RO uint32 b[31:0] - - -
REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00018000 6 RO uint32 b[31:0] - - - REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00018000 6 RO uint32 b[31:0] - - -
RAM_SCRAP 1 1 RAM data 0x00020000 512 RW uint32 b[31:0] - - - RAM_SCRAP 1 1 RAM data 0x00020000 512 RW uint32 b[31:0] - - -
AVS_ETH_0_TSE 1 1 REG status 0x00028000 1024 RO uint32 b[31:0] - - - AVS_ETH_0_TSE 1 1 REG registers 0x00028000 1024 RW uint32 b[31:0] - - -
AVS_ETH_0_REG 1 1 REG status 0x00028000 12 RO uint32 b[31:0] - - - AVS_ETH_0_REG 1 1 REG demux 0x00028000 4 RW uint32 b[16:0] - - -
AVS_ETH_0_RAM 1 1 RAM data 0x00028400 1024 RW uint32 b[31:0] - - - - - - - config_mac_address 0x00028004 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00028005 - - - b[15:0] b[47:32] - -
- - - - config_ip_address 0x00028006 1 RO uint32 b[31:0] - - -
- - - - config_udp_ctrl_port 0x00028007 1 RO uint32 b[15:0] - - -
- - - - control 0x00028008 1 RO uint32 b[31:0] - - -
- - - - control_rx_en 0x00028008 1 RO uint32 b[0:0] - - -
- - - - control_tx_en 0x00028008 1 RO uint32 b[1:1] - - -
- - - - control_tx_request 0x00028008 1 RO uint32 b[2:2] - - -
- - - - control_tx_empty 0x00028008 1 RO uint32 b[17:16] - - -
- - - - control_tx_nof_words 0x00028008 1 RO uint32 b[29:18] - - -
- - - - frame 0x00028009 1 RO uint32 b[31:0] - - -
- - - - frame_eth_mac_error 0x00028009 1 RO uint32 b[5:0] - - -
- - - - frame_mac_address_match 0x00028009 1 RO uint32 b[7:7] - - -
- - - - frame_is_arp 0x00028009 1 RO uint32 b[8:8] - - -
- - - - frame_is_ip 0x00028009 1 RO uint32 b[9:9] - - -
- - - - frame_ip_checksum_ok 0x00028009 1 RO uint32 b[10:10] - - -
- - - - frame_ip_address_match 0x00028009 1 RO uint32 b[11:11] - - -
- - - - frame_is_icmp 0x00028009 1 RO uint32 b[12:12] - - -
- - - - frame_is_udp 0x00028009 1 RO uint32 b[13:13] - - -
- - - - frame_is_udp_ctrl_port 0x00028009 1 RO uint32 b[14:14] - - -
- - - - status 0x0002800a 1 RO uint32 b[31:0] - - -
- - - - status_rx_avail 0x0002800a 1 RO uint32 b[0:0] - - -
- - - - status_tx_done 0x0002800a 1 RO uint32 b[1:1] - - -
- - - - status_tx_avail 0x0002800a 1 RO uint32 b[2:2] - - -
- - - - status_rx_empty 0x0002800a 1 RO uint32 b[17:16] - - -
- - - - status_rx_nof_words 0x0002800a 1 RO uint32 b[29:18] - - -
AVS_ETH_0_RAM 1 1 RAM data 0x00028400 1024 RO uint32 b[31:0] - - -
PIO_PPS 1 1 REG capture_cnt 0x00030000 1 RO uint32 b[29:0] - - - PIO_PPS 1 1 REG capture_cnt 0x00030000 1 RO uint32 b[29:0] - - -
- - - - stable 0x00030000 1 RO uint32 b[30:30] - - - - - - - stable 0x00030000 1 RO uint32 b[30:30] - - -
- - - - toggle 0x00030000 1 RO uint32 b[31:31] - - - - - - - toggle 0x00030000 1 RO uint32 b[31:31] - - -
......
applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
+ 29
− 3
View file @ 9e2d3015
...@@ -39,9 +39,35 @@ number_of_columns = 13 ...@@ -39,9 +39,35 @@ number_of_columns = 13
REG_FPGA_TEMP_SENS 1 1 REG temp 0x0004d2b8 1 RO uint32 b[31:0] - - - REG_FPGA_TEMP_SENS 1 1 REG temp 0x0004d2b8 1 RO uint32 b[31:0] - - -
REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0004d270 6 RO uint32 b[31:0] - - - REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0004d270 6 RO uint32 b[31:0] - - -
RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - - RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - - AVS_ETH_0_TSE 1 1 REG registers 0x00000400 1024 RW uint32 b[31:0] - - -
AVS_ETH_0_REG 1 1 REG status 0x00000c10 12 RO uint32 b[31:0] - - - AVS_ETH_0_REG 1 1 REG demux 0x00000c10 4 RW uint32 b[16:0] - - -
AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - - - - - - config_mac_address 0x00000c14 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c15 - - - b[15:0] b[47:32] - -
- - - - config_ip_address 0x00000c16 1 RO uint32 b[31:0] - - -
- - - - config_udp_ctrl_port 0x00000c17 1 RO uint32 b[15:0] - - -
- - - - control 0x00000c18 1 RO uint32 b[31:0] - - -
- - - - control_rx_en 0x00000c18 1 RO uint32 b[0:0] - - -
- - - - control_tx_en 0x00000c18 1 RO uint32 b[1:1] - - -
- - - - control_tx_request 0x00000c18 1 RO uint32 b[2:2] - - -
- - - - control_tx_empty 0x00000c18 1 RO uint32 b[17:16] - - -
- - - - control_tx_nof_words 0x00000c18 1 RO uint32 b[29:18] - - -
- - - - frame 0x00000c19 1 RO uint32 b[31:0] - - -
- - - - frame_eth_mac_error 0x00000c19 1 RO uint32 b[5:0] - - -
- - - - frame_mac_address_match 0x00000c19 1 RO uint32 b[7:7] - - -
- - - - frame_is_arp 0x00000c19 1 RO uint32 b[8:8] - - -
- - - - frame_is_ip 0x00000c19 1 RO uint32 b[9:9] - - -
- - - - frame_ip_checksum_ok 0x00000c19 1 RO uint32 b[10:10] - - -
- - - - frame_ip_address_match 0x00000c19 1 RO uint32 b[11:11] - - -
- - - - frame_is_icmp 0x00000c19 1 RO uint32 b[12:12] - - -
- - - - frame_is_udp 0x00000c19 1 RO uint32 b[13:13] - - -
- - - - frame_is_udp_ctrl_port 0x00000c19 1 RO uint32 b[14:14] - - -
- - - - status 0x00000c1a 1 RO uint32 b[31:0] - - -
- - - - status_rx_avail 0x00000c1a 1 RO uint32 b[0:0] - - -
- - - - status_tx_done 0x00000c1a 1 RO uint32 b[1:1] - - -
- - - - status_tx_avail 0x00000c1a 1 RO uint32 b[2:2] - - -
- - - - status_rx_empty 0x00000c1a 1 RO uint32 b[17:16] - - -
- - - - status_rx_nof_words 0x00000c1a 1 RO uint32 b[29:18] - - -
AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RO uint32 b[31:0] - - -
PIO_PPS 1 1 REG capture_cnt 0x0004d2e8 1 RO uint32 b[29:0] - - - PIO_PPS 1 1 REG capture_cnt 0x0004d2e8 1 RO uint32 b[29:0] - - -
- - - - stable 0x0004d2e8 1 RO uint32 b[30:30] - - - - - - - stable 0x0004d2e8 1 RO uint32 b[30:30] - - -
- - - - toggle 0x0004d2e8 1 RO uint32 b[31:31] - - - - - - - toggle 0x0004d2e8 1 RO uint32 b[31:31] - - -
......
libraries/io/eth/eth.peripheral.yaml
+ 197
− 12
View file @ 9e2d3015
...@@ -10,43 +10,228 @@ peripherals: ...@@ -10,43 +10,228 @@ peripherals:
peripheral_description: | peripheral_description: |
"The ETH module connects the 1GbE TSE [1] to the microprocessor and to streaming UDP ports [2]. The "The ETH module connects the 1GbE TSE [1] to the microprocessor and to streaming UDP ports [2]. The
packets for the streaming channels are directed based on the UDP port number and all other packets packets for the streaming channels are directed based on the UDP port number and all other packets
are transfered to the default control channel and handled by the microprocessor. are transfered to the default control channel and handled by the Nios microprocessor (unbosy.c).
The AVS_ETH_0_TSE and AVS_ETH_0_REG/demux can also be useful to access externally. The other MM
registers are set to read only, because they are controlled by the Nios and depend on the current
packet that is processed by the Nios. In case of external access, the current packet is the external
access packet. Therefore the other MM registers are less useful to access externally.
[1] https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf [1] https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf
[2] https://git.astron.nl/desp/hdl/-/blob/master/libraries/io/eth/doc/ASTRON_RP_396_eth_1gb_module.pdf" [2] https://git.astron.nl/desp/hdl/-/blob/master/libraries/io/eth/doc/ASTRON_RP_396_eth_1gb_module.pdf"
parameters:
- { name: g_nof_udp_ports, value: 4 } # = c_eth_nof_udp_ports in eth_pkg.vhd
mm_ports: mm_ports:
# MM port for registers in the TSE IP [1] # MM port for registers in the TSE IP [1]
- mm_port_name: AVS_ETH_0_TSE - mm_port_name: AVS_ETH_0_TSE
mm_port_type: REG mm_port_type: REG
mm_port_description: "Registers in the TSE IP [1], handled by the microprocessor." mm_port_description: "Registers in the TSE IP [1], handled by the Nios microprocessor."
fields: fields:
- - field_name: status - - field_name: registers
field_description: "" field_description: ""
number_of_fields: 1024 # = c_tech_tse_byte_addr_w in tech_tse_pkg.vhd number_of_fields: 1024 # = c_tech_tse_byte_addr_w in tech_tse_pkg.vhd
address_offset: 0x0 address_offset: 0x0
access_mode: RO access_mode: RW
# MM port for registers in eth_mm_registers.vhd in the ETH module [2] # MM port for registers in eth_mm_registers.vhd in the ETH module [2]
- mm_port_name: AVS_ETH_0_REG - mm_port_name: AVS_ETH_0_REG
mm_port_type: REG mm_port_type: REG
mm_port_description: "Registers in the ETH module [2], handled by the microprocessor." mm_port_span: 16 * MM_BUS_SIZE
mm_port_description: "Registers in the ETH module [2], handled by the Nios microprocessor."
fields: fields:
- - field_name: status - - field_name: demux
field_description: "" field_description: |
number_of_fields: 12 # = c_eth_reg_nof_words in eth_pkg.vhd "Demultiplex streaming (ST) data from the 1GbE link based on the UDP port.
. [31:1] = reserved,
. [16] = UDP_PORT_EN,
. [15:0] = UDP_PORT_NR
If a received frame matches the UDP port number (UDP_PORT_NR) of an enabled
(UDP_PORT_EN = 1) stream, then it is passed on to that the ST UDP offload
interface in the firmware (FW). Otherwise the received frame is kept inside
the ETH module and passed on to the Nios for further analysis."
number_of_fields: g_nof_udp_ports
address_offset: 0x0 address_offset: 0x0
mm_width: 17
access_mode: RW
- - field_name: config_mac_address
field_description: "M&C MAC address of this node."
address_offset: (g_nof_udp_ports + 0) * MM_BUS_SIZE # 4 * MM_BUS_SIZE
user_width: 48
radix: uint64
access_mode: RO
- - field_name: config_ip_address
field_description: "M&C IP address of this node."
address_offset: (g_nof_udp_ports + 2) * MM_BUS_SIZE # 6 * MM_BUS_SIZE
access_mode: RO
mm_width: 32
- - field_name: config_udp_ctrl_port
field_description: "M&C UDP port of this node."
address_offset: (g_nof_udp_ports + 3) * MM_BUS_SIZE # 7 * MM_BUS_SIZE
mm_width: 16
access_mode: RO
# Each field specified
- - field_name: control
field_description: "Nios control of Rx and Tx buffer."
address_offset: (g_nof_udp_ports + 4) * MM_BUS_SIZE # 8 * MM_BUS_SIZE
bit_offset: 0
mm_width: 32
access_mode: RO
- "control": # field_group
- field_name: tx_nof_words
field_description: "Number of words in the Tx frame, including the word align field and excluding the CRC."
address_offset: (g_nof_udp_ports + 4) * MM_BUS_SIZE # 8 * MM_BUS_SIZE
bit_offset: 18
mm_width: 12
access_mode: RO
- field_name: tx_empty
field_description: "Number of LS octets in the last word of the Tx frame that are not valid."
address_offset: (g_nof_udp_ports + 4) * MM_BUS_SIZE # 8 * MM_BUS_SIZE
bit_offset: 16
mm_width: 2
access_mode: RO
- field_name: tx_request
field_description: "Request to insert an extra Tx frame."
address_offset: (g_nof_udp_ports + 4) * MM_BUS_SIZE # 8 * MM_BUS_SIZE
bit_offset: 2
mm_width: 1
access_mode: RO
- field_name: tx_en
field_description: "Enable the ETH Tx to send out frames from the Tx frame buffer."
address_offset: (g_nof_udp_ports + 4) * MM_BUS_SIZE # 8 * MM_BUS_SIZE
bit_offset: 1
mm_width: 1
access_mode: RO
- field_name: rx_en
field_description: "Enable the ETH Rx to pass on frames to the Rx frame buffer."
address_offset: (g_nof_udp_ports + 4) * MM_BUS_SIZE # 8 * MM_BUS_SIZE
bit_offset: 0
mm_width: 1
access_mode: RO
# Each field specified
- - field_name: frame
field_description: "Information for Nios about the received frame."
address_offset: (g_nof_udp_ports + 5) * MM_BUS_SIZE # 9 * MM_BUS_SIZE
bit_offset: 0
mm_width: 32
access_mode: RO
- "frame": # field_group
- field_name: is_udp_ctrl_port
field_description: "When ‘1’ then IS_UDP=’1’ and the UDP port number matches the UDP_CTRL_PORT."
address_offset: (g_nof_udp_ports + 5) * MM_BUS_SIZE # 9 * MM_BUS_SIZE
bit_offset: 14
mm_width: 1
access_mode: RO
- field_name: is_udp
field_description: "When ‘1’ then IS_IP=’1’ and the IPv4 protocol type indicates UDP."
address_offset: (g_nof_udp_ports + 5) * MM_BUS_SIZE # 9 * MM_BUS_SIZE
bit_offset: 13
mm_width: 1
access_mode: RO
- field_name: is_icmp
field_description: "When ‘1’ then IS_IP=’1’ and the IPv4 protocol type indicates ICMP."
address_offset: (g_nof_udp_ports + 5) * MM_BUS_SIZE # 9 * MM_BUS_SIZE
bit_offset: 12
mm_width: 1
access_mode: RO
- field_name: ip_address_match
field_description: "When ‘1’ then IS_IP=’1’ and the IPv4 address matches this node IP_ADDRESS."
address_offset: (g_nof_udp_ports + 5) * MM_BUS_SIZE # 9 * MM_BUS_SIZE
bit_offset: 11
mm_width: 1
access_mode: RO
- field_name: ip_checksum_ok
field_description: "When ‘1’ then IS_IP=’1’ and the IPv4 header checksum is OK."
address_offset: (g_nof_udp_ports + 5) * MM_BUS_SIZE # 9 * MM_BUS_SIZE
bit_offset: 10
mm_width: 1
access_mode: RO
- field_name: is_ip
field_description: "When ‘1’ then the Ethernet type indicates IPv4."
address_offset: (g_nof_udp_ports + 5) * MM_BUS_SIZE # 9 * MM_BUS_SIZE
bit_offset: 9
mm_width: 1
access_mode: RO
- field_name: is_arp
field_description: "When ‘1’ then the Ethernet type indicates ARP."
address_offset: (g_nof_udp_ports + 5) * MM_BUS_SIZE # 9 * MM_BUS_SIZE
bit_offset: 8
mm_width: 1
access_mode: RO
- field_name: mac_address_match
field_description: "When ‘1’ then the DST_MAC address matches this node MAC_ADDRESS."
address_offset: (g_nof_udp_ports + 5) * MM_BUS_SIZE # 9 * MM_BUS_SIZE
bit_offset: 7
mm_width: 1
access_mode: RO
- field_name: eth_mac_error
field_description: |
"When ‘0’ then OK, else TSE IP error indication:
[5] = collision error (can only occur in half duplex mode)
[4] = PHY error on GMII
[3] = receive frame truncated due to FIFO overflow
[2] = CRC-32 error
[1] = invalid length
[0] = OR of [1:5]"
address_offset: (g_nof_udp_ports + 5) * MM_BUS_SIZE # 9 * MM_BUS_SIZE
bit_offset: 0
mm_width: 6
access_mode: RO
# Each field specified
- - field_name: status
field_description: "Information for Nios about the Rx and Tx buffer."
address_offset: (g_nof_udp_ports + 6) * MM_BUS_SIZE # 10 * MM_BUS_SIZE
bit_offset: 0
mm_width: 32
access_mode: RO
- "status": # field_group
- field_name: rx_nof_words
field_description: "Number of words in the Rx frame, including the word align field and including the CRC."
address_offset: (g_nof_udp_ports + 6) * MM_BUS_SIZE # 10 * MM_BUS_SIZE
bit_offset: 18
mm_width: 12
access_mode: RO
- field_name: rx_empty
field_description: "Number of octets in the last word of the Rx frame that are not valid."
address_offset: (g_nof_udp_ports + 6) * MM_BUS_SIZE # 10 * MM_BUS_SIZE
bit_offset: 16
mm_width: 2
access_mode: RO
- field_name: tx_avail
field_description: "When ‘1’ then the Tx buffer is available for inserting a Tx frame."
address_offset: (g_nof_udp_ports + 6) * MM_BUS_SIZE # 10 * MM_BUS_SIZE
bit_offset: 2
mm_width: 1
access_mode: RO
- field_name: tx_done
field_description: "When ‘1’ then the Tx frame in the Tx buffer has been send."
address_offset: (g_nof_udp_ports + 6) * MM_BUS_SIZE # 10 * MM_BUS_SIZE
bit_offset: 1
mm_width: 1
access_mode: RO
- field_name: rx_avail
field_description: "When ‘1’ then there is a new Rx frame available in the Rx buffer."
address_offset: (g_nof_udp_ports + 6) * MM_BUS_SIZE # 10 * MM_BUS_SIZE
bit_offset: 0
mm_width: 1
access_mode: RO access_mode: RO
# MM port for ETH packet packet buffers in eth.vhd # MM port for ETH packet packet buffers in eth.vhd
- mm_port_name: AVS_ETH_0_RAM - mm_port_name: AVS_ETH_0_RAM
mm_port_type: RAM mm_port_type: RAM
mm_port_description: | mm_port_description: |
"Buffer RAM for request packets (Rx) and response packets (Tx) via 1GbE, used by the microprocessor "Buffer RAM for request packets (Rx) and response packets (Tx) via 1GbE, used by the Nios microprocessor
to receive and transmit packets via the ETH module." to receive and transmit packets via the ETH module."
fields: fields:
- - field_name: data - - field_name: data
field_description: "Data 32b-word." field_description: "Data 32b-word."
number_of_fields: 1024 # = c_eth_ram_nof_words in eth_pkg.vhd number_of_fields: 1024 # = c_eth_ram_nof_words in eth_pkg.vhd
access_mode: RO
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