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Commit 9cdcf1ca authored by Pepping's avatar Pepping
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- MOved bsn monitor into node 

- connect datapath clock backinto io_ddr at node level. 
- removed array from ddr port map
parent 24aecd2d
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applications/unb1_reorder/src/vhdl/node_unb1_reorder.vhd
+ 151
− 123
View file @ 9cdcf1ca
...@@ -40,42 +40,46 @@ ENTITY node_unb1_reorder IS ...@@ -40,42 +40,46 @@ ENTITY node_unb1_reorder IS
g_in_dat_w : POSITIVE := 8; g_in_dat_w : POSITIVE := 8;
g_ena_pre_transp : BOOLEAN := TRUE; g_ena_pre_transp : BOOLEAN := TRUE;
g_reorder_seq : t_reorder_seq := c_reorder_seq g_reorder_seq : t_reorder_seq := c_reorder_seq
); );
PORT ( PORT (
-- System -- System
mm_rst : IN STD_LOGIC; mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC; mm_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC; dp_rst : IN STD_LOGIC;
dp_clk : IN STD_LOGIC; dp_clk : IN STD_LOGIC;
ddr_ref_clk : IN STD_LOGIC; ddr_ref_clk : IN STD_LOGIC;
ddr_ref_rst : IN STD_LOGIC; ddr_ref_rst : IN STD_LOGIC;
-- Clock outputs -- Clock outputs
ddr_out_clk : OUT STD_LOGIC; ddr_out_clk : OUT STD_LOGIC;
ddr_out_rst : OUT STD_LOGIC; ddr_out_rst : OUT STD_LOGIC;
-- ST sinks
in_siso_arr : OUT t_dp_siso_arr(g_nof_streams -1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams -1 DOWNTO 0);
-- ST source
out_siso_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
-- IO DDR register map
reg_io_ddr_mosi : IN t_mem_mosi;
reg_io_ddr_miso : OUT t_mem_miso;
-- Reorder transpose
ram_ss_ss_transp_mosi : IN t_mem_mosi;
ram_ss_ss_transp_miso : OUT t_mem_miso;
-- ST sinks -- BSN Monitor
in_siso_arr : OUT t_dp_siso_arr(g_nof_streams -1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); reg_bsn_monitor_mosi : IN t_mem_mosi;
in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams -1 DOWNTO 0); reg_bsn_monitor_miso : OUT t_mem_miso;
-- ST source
out_siso_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
-- IO DDR register map
reg_io_ddr_mosi : IN t_mem_mosi;
reg_io_ddr_miso : OUT t_mem_miso;
-- Reorder transpose
ram_ss_ss_transp_mosi : IN t_mem_mosi;
ram_ss_ss_transp_miso : OUT t_mem_miso;
-- SO-DIMM Memory Bank I -- SO-DIMM Memory Bank I
MB_I_IN : IN t_tech_ddr3_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0); MB_I_IN : IN t_tech_ddr3_phy_in;
MB_I_IO : INOUT t_tech_ddr3_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0); MB_I_IO : INOUT t_tech_ddr3_phy_io;
MB_I_OU : OUT t_tech_ddr3_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0) MB_I_OU : OUT t_tech_ddr3_phy_ou
); );
END node_unb1_reorder; END node_unb1_reorder;
...@@ -95,85 +99,54 @@ ARCHITECTURE str OF node_unb1_reorder IS ...@@ -95,85 +99,54 @@ ARCHITECTURE str OF node_unb1_reorder IS
CONSTANT c_rd_fifo_depth : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO. CONSTANT c_rd_fifo_depth : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
CONSTANT c_rd_data_w : NATURAL := c_data_w; CONSTANT c_rd_data_w : NATURAL := c_data_w;
-- CONSTANT c_mts : NATURAL := 800;--1066; --800
-- CONSTANT c_phy : NATURAL := 1;
-- CONSTANT c_nof_blk_per_sync : POSITIVE := 1600000;
-- CONSTANT c_ddr3_seq_conf : t_ddr3_seq := (g_reorder_seq.wr_chunksize,
-- 1,
-- g_reorder_seq.rd_chunksize,
-- g_reorder_seq.rd_nof_chunks,
-- g_reorder_seq.gapsize,
-- g_reorder_seq.nof_blocks);
--
-- Signals to interface with the DDR conroller and memory model. -- Signals to interface with the DDR conroller and memory model.
SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso; SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi; SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
SIGNAL to_mem_siso : t_dp_siso := c_dp_siso_rdy; SIGNAL to_mem_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL to_mem_sosi : t_dp_sosi; SIGNAL to_mem_sosi : t_dp_sosi;
SIGNAL from_mem_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL from_mem_sosi : t_dp_sosi;
SIGNAL ctlr_clk : STD_LOGIC; SIGNAL from_mem_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL ctlr_rst : STD_LOGIC; SIGNAL from_mem_sosi : t_dp_sosi;
BEGIN SIGNAL ddr_out_clk_i : STD_LOGIC;
SIGNAL ddr_out_rst_i : STD_LOGIC;
SIGNAL out_sosi_arr_i : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
------------------------------------------------------------------------------ SIGNAL bsn_sosi_arr : t_dp_sosi_arr(3 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
-- OLD DDR3 TRANSPOSE
------------------------------------------------------------------------------
-- u_ddr3_T: ENTITY ddr3_lib.ddr3_transpose
-- GENERIC MAP(
-- g_sim => g_sim,
-- g_nof_streams => g_nof_streams,
-- g_in_dat_w => g_in_dat_w,
-- g_frame_size_in => g_reorder_seq.wr_chunksize,
-- g_frame_size_out => g_reorder_seq.wr_chunksize,
-- g_nof_blk_per_sync => c_nof_blk_per_sync,
-- g_use_complex => TRUE,
-- g_ena_pre_transp => g_ena_pre_transp,
-- g_phy => c_phy,
-- g_mts => c_mts,
-- g_ddr3_seq => c_ddr3_seq_conf
-- )
-- PORT MAP (
-- mm_rst => mm_rst,
-- mm_clk => mm_clk,
--
-- dp_ref_clk => ddr_ref_clk,
-- dp_ref_rst => ddr_ref_rst,
--
-- dp_clk => dp_clk,
-- dp_rst => dp_rst,
--
-- dp_out_clk => ddr_out_clk,
-- dp_out_rst => ddr_out_rst,
--
-- snk_out_arr => in_siso_arr,
-- snk_in_arr => in_sosi_arr,
--
-- reg_io_ddr_mosi => reg_io_ddr_mosi,
-- reg_io_ddr_miso => reg_io_ddr_miso,
--
-- -- ST source
-- src_in_arr => out_siso_arr,
-- src_out_arr => out_sosi_arr,
--
-- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
-- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
--
-- ser_term_ctrl_out => OPEN,
-- par_term_ctrl_out => OPEN,
--
-- ser_term_ctrl_in => OPEN,
-- par_term_ctrl_in => OPEN,
--
-- phy_in => MB_I_in(0),
-- phy_io => MB_I_io(0),
-- phy_ou => MB_I_ou(0)
-- );
BEGIN
u_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
GENERIC MAP (
g_nof_streams => 4, -- Check one input and one output stream
g_cross_clock_domain => TRUE,
g_bsn_w => c_dp_stream_bsn_w,
g_cnt_sop_w => c_word_w,
g_cnt_valid_w => c_word_w,
g_log_first_bsn => TRUE
)
PORT MAP (
-- Memory-mapped clock domain
mm_rst => mm_rst,
mm_clk => mm_clk,
reg_mosi => reg_bsn_monitor_mosi,
reg_miso => reg_bsn_monitor_miso,
-- Streaming clock domain
dp_rst => ddr_out_rst_i,
dp_clk => ddr_out_clk_i,
in_siso_arr => (OTHERS=>c_dp_siso_rdy),
in_sosi_arr => bsn_sosi_arr
);
bsn_sosi_arr(0) <= in_sosi_arr(0);
bsn_sosi_arr(1) <= to_mem_sosi;
bsn_sosi_arr(2) <= from_mem_sosi;
bsn_sosi_arr(3) <= out_sosi_arr_i(0);
out_sosi_arr <= out_sosi_arr_i;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- TRANSPOSE UNIT -- TRANSPOSE UNIT
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -192,8 +165,8 @@ BEGIN ...@@ -192,8 +165,8 @@ BEGIN
mm_rst => mm_rst, mm_rst => mm_rst,
mm_clk => mm_clk, mm_clk => mm_clk,
dp_rst => dp_rst, dp_rst => ddr_out_rst_i,
dp_clk => dp_clk, dp_clk => ddr_out_clk_i,
-- ST sink -- ST sink
snk_out_arr => in_siso_arr, snk_out_arr => in_siso_arr,
...@@ -201,7 +174,7 @@ BEGIN ...@@ -201,7 +174,7 @@ BEGIN
-- ST source -- ST source
src_in_arr => out_siso_arr, src_in_arr => out_siso_arr,
src_out_arr => out_sosi_arr, src_out_arr => out_sosi_arr_i,
ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi, ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
ram_ss_ss_transp_miso => ram_ss_ss_transp_miso, ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
...@@ -222,7 +195,6 @@ BEGIN ...@@ -222,7 +195,6 @@ BEGIN
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- DDR3 MODULE 0, MB_I -- DDR3 MODULE 0, MB_I
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
u_ddr_mem_ctrl : ENTITY io_ddr_lib.io_ddr u_ddr_mem_ctrl : ENTITY io_ddr_lib.io_ddr
GENERIC MAP( GENERIC MAP(
g_technology => g_tech_select_default, g_technology => g_tech_select_default,
...@@ -243,11 +215,11 @@ BEGIN ...@@ -243,11 +215,11 @@ BEGIN
ctlr_ref_rst => ddr_ref_rst, ctlr_ref_rst => ddr_ref_rst,
-- DDR controller clock domain -- DDR controller clock domain
ctlr_clk_out => ddr_out_clk, -- output clock of the ddr controller is used as DP clk. ctlr_clk_out => ddr_out_clk_i, -- output clock of the ddr controller is used as DP clk.
ctlr_rst_out => ddr_out_rst, ctlr_rst_out => ddr_out_rst_i,
ctlr_clk_in => dp_clk, ctlr_clk_in => ddr_out_clk_i,
ctlr_rst_in => dp_rst, ctlr_rst_in => ddr_out_rst_i,
-- MM clock + reset -- MM clock + reset
mm_rst => mm_rst, mm_rst => mm_rst,
...@@ -257,25 +229,24 @@ BEGIN ...@@ -257,25 +229,24 @@ BEGIN
reg_io_ddr_mosi => reg_io_ddr_mosi, reg_io_ddr_mosi => reg_io_ddr_mosi,
reg_io_ddr_miso => reg_io_ddr_miso, reg_io_ddr_miso => reg_io_ddr_miso,
-- Driver clock domain -- Driver clock domain
dvr_clk => dp_clk, dvr_clk => ddr_out_clk_i,
dvr_rst => dp_rst, dvr_rst => ddr_out_rst_i,
dvr_miso => ctlr_dvr_miso, dvr_miso => ctlr_dvr_miso,
dvr_mosi => ctlr_dvr_mosi, dvr_mosi => ctlr_dvr_mosi,
-- Write FIFO clock domain -- Write FIFO clock domain
wr_clk => dp_clk, wr_clk => ddr_out_clk_i,
wr_rst => dp_rst, wr_rst => ddr_out_rst_i,
wr_fifo_usedw => OPEN, wr_fifo_usedw => OPEN,
wr_sosi => to_mem_sosi, wr_sosi => to_mem_sosi,
wr_siso => to_mem_siso, wr_siso => to_mem_siso,
-- Read FIFO clock domain -- Read FIFO clock domain
rd_clk => dp_clk, rd_clk => ddr_out_clk_i,
rd_rst => dp_rst, rd_rst => ddr_out_rst_i,
rd_fifo_usedw => OPEN, rd_fifo_usedw => OPEN,
rd_sosi => from_mem_sosi, rd_sosi => from_mem_sosi,
...@@ -284,10 +255,67 @@ BEGIN ...@@ -284,10 +255,67 @@ BEGIN
term_ctrl_out => OPEN, term_ctrl_out => OPEN,
term_ctrl_in => OPEN, term_ctrl_in => OPEN,
phy3_in => MB_I_IN(0), phy3_in => MB_I_IN,
phy3_io => MB_I_IO(0), phy3_io => MB_I_IO,
phy3_ou => MB_I_OU(0) phy3_ou => MB_I_OU
); );
ddr_out_clk <= ddr_out_clk_i;
ddr_out_rst <= ddr_out_rst_i;
------------------------------------------------------------------------------
-- OLD DDR3 TRANSPOSE
------------------------------------------------------------------------------
-- u_ddr3_T: ENTITY ddr3_lib.ddr3_transpose
-- GENERIC MAP(
-- g_sim => g_sim,
-- g_nof_streams => g_nof_streams,
-- g_in_dat_w => g_in_dat_w,
-- g_frame_size_in => g_reorder_seq.wr_chunksize,
-- g_frame_size_out => g_reorder_seq.wr_chunksize,
-- g_nof_blk_per_sync => c_nof_blk_per_sync,
-- g_use_complex => TRUE,
-- g_ena_pre_transp => g_ena_pre_transp,
-- g_phy => c_phy,
-- g_mts => c_mts,
-- g_ddr3_seq => c_ddr3_seq_conf
-- )
-- PORT MAP (
-- mm_rst => mm_rst,
-- mm_clk => mm_clk,
--
-- dp_ref_clk => ddr_ref_clk,
-- dp_ref_rst => ddr_ref_rst,
--
-- dp_clk => dp_clk,
-- dp_rst => dp_rst,
--
-- dp_out_clk => ddr_out_clk,
-- dp_out_rst => ddr_out_rst,
--
-- snk_out_arr => in_siso_arr,
-- snk_in_arr => in_sosi_arr,
--
-- reg_io_ddr_mosi => reg_io_ddr_mosi,
-- reg_io_ddr_miso => reg_io_ddr_miso,
--
-- -- ST source
-- src_in_arr => out_siso_arr,
-- src_out_arr => out_sosi_arr,
--
-- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
-- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
--
-- ser_term_ctrl_out => OPEN,
-- par_term_ctrl_out => OPEN,
--
-- ser_term_ctrl_in => OPEN,
-- par_term_ctrl_in => OPEN,
--
-- phy_in => MB_I_in(0),
-- phy_io => MB_I_io(0),
-- phy_ou => MB_I_ou(0)
-- );
END str; END str;
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