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Commit 9c821e0b authored by Pepping's avatar Pepping
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-replaced sopc by mmm 

- Updated libraries fro RadioHDL.
parent ed138b80
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boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
+ 154
− 223
View file @ 9c821e0b
......@@ -19,36 +19,32 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb_common_lib, dp_lib;
LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE unb_common_lib.unb_common_pkg.ALL;
USE unb_common_lib.unb_peripherals_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_network_total_header_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE eth_lib.eth_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE tech_tse_lib.tb_tech_tse_pkg.ALL;
ENTITY fn_terminal_db IS
ENTITY unb1_fn_terminal_db IS
GENERIC (
-- General
g_sim : BOOLEAN := FALSE;
g_rev_multi_unb : BOOLEAN := FALSE; -- Set to TRUE by Quartus revision fn_terminal_db_rev_multi.
g_design_name : STRING := "fn_terminal_db"; -- Set to "fn_terminal_db_rev_multi_unb" by revision fn_terminal_db_rev_multi
g_fw_version : t_unb_fw_version := (1, 0); -- firmware version x.y
-- Use PHY Interface
-- TYPE t_c_unb_use_phy IS RECORD
-- eth1g : NATURAL;
-- tr_front: NATURAL;
-- tr_mesh : NATURAL;
-- tr_back : NATURAL;
-- ddr3_I : NATURAL;
-- ddr3_II : NATURAL;
-- adc : NATURAL;
-- wdi : NATURAL;
-- END RECORD;
g_use_phy : t_c_unb_use_phy := (1, 0, 1, 0, 0, 0, 0, 1);
g_tr_mesh : t_c_unb_tr := c_unb_tr_mesh;
g_aux : t_c_unb_aux := c_unb_aux
g_design_name : STRING := "unb1_fn_terminal_db"; -- Set to "fn_terminal_db_rev_multi_unb" by revision fn_terminal_db_rev_multi
g_design_note : STRING := "UNUSED";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
);
PORT (
-- GENERAL
......@@ -59,9 +55,9 @@ ENTITY fn_terminal_db IS
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
VERSION : IN STD_LOGIC_VECTOR(g_aux.version_w-1 DOWNTO 0);
ID : IN STD_LOGIC_VECTOR(g_aux.id_w-1 DOWNTO 0);
TESTIO : INOUT STD_LOGIC_VECTOR(g_aux.testio_w-1 DOWNTO 0);
VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
sens_sc : INOUT STD_LOGIC;
......@@ -77,23 +73,26 @@ ENTITY fn_terminal_db IS
SB_CLK : IN STD_LOGIC := '0'; -- TR clock FN-BN (mesh)
-- Serial I/O
FN_BN_0_TX : OUT STD_LOGIC_VECTOR(g_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_0_RX : IN STD_LOGIC_VECTOR(g_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_1_TX : OUT STD_LOGIC_VECTOR(g_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_1_RX : IN STD_LOGIC_VECTOR(g_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_2_TX : OUT STD_LOGIC_VECTOR(g_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_2_RX : IN STD_LOGIC_VECTOR(g_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_3_TX : OUT STD_LOGIC_VECTOR(g_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_3_RX : IN STD_LOGIC_VECTOR(g_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0')
FN_BN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0')
);
END fn_terminal_db;
END unb1_fn_terminal_db;
ARCHITECTURE str OF fn_terminal_db IS
CONSTANT c_use_mesh : BOOLEAN := g_use_phy.tr_mesh=1;
ARCHITECTURE str OF unb1_fn_terminal_db IS
CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, 0, 1, 0, 0, 0, 0, 1);
CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 0); -- firmware version x.y
CONSTANT c_use_mesh : BOOLEAN := c_use_phy.tr_mesh=1;
CONSTANT c_mesh_mon_select : NATURAL := 1; -- > 0 = enable SOSI data buffers monitor via MM
CONSTANT c_mesh_mon_nof_words : NATURAL := c_unb_mm_reg_default.ram_diag_db_buf_size; -- = 1024
CONSTANT c_mesh_mon_nof_words : NATURAL := c_unb1_board_peripherals_mm_reg_default.ram_diag_db_buf_size; -- = 1024
CONSTANT c_mesh_mon_use_sync : BOOLEAN := TRUE; -- when TRUE use dp_pps to trigger the data buffer capture, else new data capture after read access of last data word
CONSTANT c_reg_diag_db_adr_w : NATURAL := 5;
......@@ -101,16 +100,18 @@ ARCHITECTURE str OF fn_terminal_db IS
-- System
SIGNAL cs_sim : STD_LOGIC;
SIGNAL xo_clk : STD_LOGIC;
SIGNAL xo_rst : STD_LOGIC;
SIGNAL xo_rst_n : STD_LOGIC;
SIGNAL cal_clk : STD_LOGIC;
SIGNAL mm_clk : STD_LOGIC;
SIGNAL mm_locked : STD_LOGIC;
SIGNAL mm_rst : STD_LOGIC;
SIGNAL cal_clk : STD_LOGIC;
SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC;
SIGNAL dp_pps : STD_LOGIC;
SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb_nof_chip_w-1 DOWNTO 0); -- [2:0], so range 0-3 for FN and range 4-7 BN
SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0); -- [2:0], so range 0-3 for FN and range 4-7 BN
-- PIOs
SIGNAL pout_debug_wave : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
......@@ -145,8 +146,8 @@ ARCHITECTURE str OF fn_terminal_db IS
SIGNAL eth1g_ram_miso : t_mem_miso;
-- tr_mesh
SIGNAL tx_serial_2arr : t_unb_mesh_sl_2arr; -- Tx
SIGNAL rx_serial_2arr : t_unb_mesh_sl_2arr; -- Rx support for diagnostics
SIGNAL tx_serial_2arr : t_unb1_board_mesh_sl_2arr; -- Tx
SIGNAL rx_serial_2arr : t_unb1_board_mesh_sl_2arr; -- Rx support for diagnostics
-- MM tr_nonbonded with diagnostics
SIGNAL reg_tr_nonbonded_mosi : t_mem_mosi := c_mem_mosi_rst;
......@@ -171,198 +172,60 @@ ARCHITECTURE str OF fn_terminal_db IS
BEGIN
-----------------------------------------------------------------------------
-- SOPC system
-----------------------------------------------------------------------------
u_sopc : ENTITY work.sopc_fn_terminal_db
PORT MAP (
-- 1) global signals:
clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
reset_n => xo_rst_n,
mm_clk => mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
-- the_altpll_0
areset_to_the_altpll_0 => '0',
locked_from_the_altpll_0 => mm_locked,
phasedone_from_the_altpll_0 => OPEN,
-- the_avs_eth_0
coe_clk_export_from_the_avs_eth_0 => OPEN,
coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
-- the_reg_unb_sens
coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_unb_sens => OPEN,
coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_unb_sens => OPEN,
coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_tr_nonbonded_mesh
coe_address_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.address(c_unb_mm_reg_default.reg_tr_nonbonded_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_tr_nonbonded_mesh => OPEN,
coe_read_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.rd,
coe_readdata_export_to_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_tr_nonbonded_mesh => OPEN,
coe_write_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wr,
coe_writedata_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diagnostics_mesh
coe_address_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.address(c_unb_mm_reg_default.reg_diagnostics_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_diagnostics_mesh => OPEN,
coe_read_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.rd,
coe_readdata_export_to_the_reg_diagnostics_mesh => reg_diagnostics_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_diagnostics_mesh => OPEN,
coe_write_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wr,
coe_writedata_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_diag_data_buffer
coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_unb_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diag_data_buffer
coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_reg_diag_db_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_diag_data_buffer_mesh
coe_address_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.address(c_unb_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_ram_diag_data_buffer_mesh => OPEN,
coe_read_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.rd,
coe_readdata_export_to_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_ram_diag_data_buffer_mesh => OPEN,
coe_write_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.wr,
coe_writedata_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_bsn_monitor
coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_unb_mm_reg_default.reg_bsn_monitor_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_bsn_monitor => OPEN,
coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_bsn_monitor => OPEN,
coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_debug_wave
out_port_from_the_pio_debug_wave => pout_debug_wave,
-- the_pio_pps
in_port_to_the_pio_pps => pin_pps,
-- the_pio_system_info: actually a avs_common_mm instance
coe_clk_export_from_the_pio_system_info => OPEN,
coe_reset_export_from_the_pio_system_info => OPEN,
coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_rom_system_info
coe_clk_export_from_the_rom_system_info => OPEN,
coe_reset_export_from_the_rom_system_info => OPEN,
coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_wdi
out_port_from_the_pio_wdi => pout_wdi,
-- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
coe_clk_export_from_the_reg_wdi => OPEN,
coe_reset_export_from_the_reg_wdi => OPEN,
coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0)
);
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : ENTITY unb_common_lib.ctrl_unb_common
u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
GENERIC MAP (
-- General
g_design_name => g_design_name,
g_fw_version => g_fw_version,
-- Use PHY Interface
g_use_phy => g_use_phy,
-- Auxiliary Interface
g_aux => g_aux
g_sim => g_sim,
g_design_name => g_design_name,
g_design_note => g_design_note,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn,
g_fw_version => c_fw_version,
g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
g_use_phy => c_use_phy,
g_aux => c_unb1_board_aux
)
PORT MAP (
--
-- >>> SOPC system with conduit peripheral MM bus
--
-- System
-- Clock an reset signals
cs_sim => cs_sim,
xo_clk => xo_clk,
xo_rst => xo_rst,
xo_rst_n => xo_rst_n,
mm_clk => mm_clk,
mm_locked => mm_locked,
mm_rst => mm_rst,
dp_rst => dp_rst,
dp_clk => dp_clk,
dp_pps => dp_pps,
dp_pps => OPEN,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
this_chip_id => this_chip_id,
-- PIOs
pout_debug_wave => pout_debug_wave,
pout_wdi => pout_wdi,
-- Toggle WDI
pout_wdi => pout_wdi,
pin_pps => pin_pps,
-- System_info
-- MM buses
-- . Manual WDI override
reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso,
-- . System_info
reg_unb_system_info_mosi => reg_unb_system_info_mosi,
reg_unb_system_info_miso => reg_unb_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi,
rom_unb_system_info_miso => rom_unb_system_info_miso,
-- Manual WDI override
reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso,
-- UniBoard I2C sensors
-- . UniBoard I2C sensors
reg_unb_sens_mosi => reg_unb_sens_mosi,
reg_unb_sens_miso => reg_unb_sens_miso,
reg_unb_sens_miso => reg_unb_sens_miso,
-- eth1g
eth1g_tse_clk => eth1g_tse_clk,
eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
......@@ -371,34 +234,102 @@ BEGIN
eth1g_reg_interrupt => eth1g_reg_interrupt,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
--
-- >>> Ctrl FPGA pins
--
-- General
-- FPGA pins
-- . General
CLK => CLK,
PPS => PPS,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- Others
-- . Others
VERSION => VERSION,
ID => ID,
TESTIO => TESTIO,
-- I2C Interface to Sensors
-- . I2C Interface to Sensors
sens_sc => sens_sc,
sens_sd => sens_sd,
sens_sd => sens_sd,
-- . 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT
);
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : ENTITY work.mmm_unb1_fn_terminal_db
GENERIC MAP (
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr
)
PORT MAP(
xo_clk => xo_clk,
xo_rst_n => xo_rst_n,
xo_rst => xo_rst,
mm_rst => mm_rst,
mm_clk => mm_clk,
mm_locked => mm_locked,
cal_clk => cal_clk,
-- PIOs
pout_wdi => pout_wdi,
pin_pps => pin_pps,
-- Manual WDI override
reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso,
-- system_info
reg_unb_system_info_mosi => reg_unb_system_info_mosi,
reg_unb_system_info_miso => reg_unb_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi,
rom_unb_system_info_miso => rom_unb_system_info_miso,
-- UniBoard I2C sensors
reg_unb_sens_mosi => reg_unb_sens_mosi,
reg_unb_sens_miso => reg_unb_sens_miso,
-- eth1g
eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
eth1g_reg_mosi => eth1g_reg_mosi,
eth1g_reg_miso => eth1g_reg_miso,
eth1g_reg_interrupt => eth1g_reg_interrupt,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
-- . tr_nonbonded
reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
reg_diagnostics_mosi => reg_diagnostics_mosi,
reg_diagnostics_miso => reg_diagnostics_miso,
-- . diag_data_buffer
ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
ram_diag_data_buf_miso => ram_diag_data_buf_miso,
reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-- . diag_data_buffer_mesh
ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
-- . bsn_monitor
reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
reg_bsn_monitor_miso => reg_bsn_monitor_miso
);
-----------------------------------------------------------------------------
-- Node functioon: Terminals and data buffer
-----------------------------------------------------------------------------
u_node_fn_terminal_db : ENTITY work.node_fn_terminal_db
u_node_unb1_fn_terminal_db : ENTITY work.node_unb1_fn_terminal_db
GENERIC MAP(
g_multi_unb => g_rev_multi_unb,
-- Terminals interface
......@@ -407,7 +338,7 @@ BEGIN
g_mesh_mon_nof_words => c_mesh_mon_nof_words,
g_mesh_mon_use_sync => c_mesh_mon_use_sync,
-- Auxiliary Interface
g_aux => c_unb_aux
g_aux => c_unb1_board_aux
)
PORT MAP(
-- System
......@@ -447,14 +378,14 @@ BEGIN
-----------------------------------------------------------------------------
-- Mesh I/O
-----------------------------------------------------------------------------
no_tr_mesh : IF g_use_phy.tr_mesh=0 GENERATE
no_tr_mesh : IF c_use_phy.tr_mesh=0 GENERATE
rx_serial_2arr <= (OTHERS=>(OTHERS=>'0'));
END GENERATE;
gen_tr_mesh : IF g_use_phy.tr_mesh/=0 GENERATE
u_mesh_io : ENTITY unb_common_lib.unb_mesh_io
gen_tr_mesh : IF c_use_phy.tr_mesh/=0 GENERATE
u_mesh_io : ENTITY unb1_board_lib.unb1_board_mesh_io
GENERIC MAP (
g_bus_w => g_tr_mesh.bus_w
g_bus_w => c_unb1_board_tr_mesh.bus_w
)
PORT MAP (
tx_serial_2arr => tx_serial_2arr,
......
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