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Commit 9c5728f8 authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
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Make transceiver reset channels work independantly

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boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ 26
− 16
View file @ 9c5728f8
......@@ -21,24 +21,24 @@
###############################################################################
# Constrain the input I/O path
#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2c_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2c_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
# Constrain the output I/O path
#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2c_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2c_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
# False path the PPS to DDIO:
#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2c_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 3 [get_ports {PPS}]
#set_false_path -from {PPS} -to {ctrl_unb2c_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}; set_false_path -from {PPS} -to {ctrl_unb2c_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}
#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 3 [get_ports {PPS}]
#set_false_path -from {PPS} -to {ctrl_unb2_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}; set_false_path -from {PPS} -to {ctrl_unb2_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}
#set_false_path -from [get_ports {PPS}] -to [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2c_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}]
#set_false_path -from [get_ports {PPS}] -to [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}]
#set_input_delay -min -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2c_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 2 [get_ports {ctrl_unb2c_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
#set_input_delay -max -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2c_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 4 [get_ports {ctrl_unb2c_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
#set_input_delay -min -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 2 [get_ports {ctrl_unb2_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
#set_input_delay -max -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 4 [get_ports {ctrl_unb2_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
#set_false_path -from {PPS} -to {ctrl_unb2c_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio*}
#set_false_path -from {PPS} -to {ctrl_unb2_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio*}
......@@ -70,17 +70,27 @@ set_clock_groups -asynchronous -group [get_clocks pll_clk125]
set_clock_groups -asynchronous -group [get_clocks pll_clk200]
set_clock_groups -asynchronous -group [get_clocks pll_clk200p]
set_clock_groups -asynchronous -group [get_clocks pll_clk400]
# Isolate the 200MHz dp_clk
set_clock_groups -asynchronous -group [get_clocks {*|u_ctrl_unb2_board|\gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}]
# FPLL outputs
set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk0}]
set_clock_groups -asynchronous -group [get_clocks {*mac_clock*xcvr_fpll_a10_0|outclk0}]
set_clock_groups -asynchronous -group [get_clocks {*dp_clk*xcvr_fpll_a10_0|outclk0}]
set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk1}]
# Three of these have been removed because they cut paths between the PHY and MAC, and between the 156.25MHz
# and 132.5MHz paths within the MAC. The other two asynchronous groups will be checked to see if they are
# needed
#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk0}]
#set_clock_groups -asynchronous -group [get_clocks {*mac_clock*xcvr_fpll_a10_0|outclk0}]
#set_clock_groups -asynchronous -group [get_clocks {*dp_clk*xcvr_fpll_a10_0|outclk0}]
#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk1}]
set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk3}]
# Cut paths used in signal taps (temporary 06-09-2019 - will be removed for production designs)
set_false_path -from [get_clocks {*u_tech_10gbase_r|\gen_ip_arria10_e1sg:u0|\gen_phy_24:u_ip_arria10_e1sg_phy_10gbase_r_24|xcvr_native_a10_0|g_xcvr_native_insts*|avmmclk}] -to [get_clocks {u_tech_pll_xgmii_mac_clocks|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}];
set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk}]
# False path from mm_clk to MAC clocks
set_false_path -from [get_clocks {*|u_ctrl_unb2_board|\gen_mm_clk_hardware:u_unb2_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk1}] -to [get_clocks {*|u_tech_pll_xgmii_mac_clocks|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}]
# Seems harmless to remove this
#set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk}]
#set_false_path -from {*u_rst200|u_async|din_meta[2]} -to {*FIFOram*}
......
libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+ 12
− 5
View file @ 9c5728f8
......@@ -89,6 +89,9 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL pll_reset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL xcvr_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL rx_avs_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL rxlink_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL rxframe_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL rx_avs_rst_n_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL rxlink_rst_n_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL rxframe_rst_n_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
......@@ -249,7 +252,6 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
component ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12_cmp is
port (
clock : in std_logic := 'X'; -- clk
pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
reset : in std_logic := 'X'; -- reset
rx_analogreset : out std_logic_vector(11 downto 0); -- rx_analogreset
rx_cal_busy : in std_logic_vector(11 downto 0) := (others => 'X'); -- rx_cal_busy
......@@ -395,12 +397,17 @@ BEGIN
reset_out2 => open,
reset_out3 => open,
reset_out4 => open,
reset_out5 => rx_avs_rst_n_arr(i),
reset_out6 => rxlink_rst_n_arr(i),
reset_out7 => rxframe_rst_n_arr(i)
reset_out5 => rx_avs_rst_arr(i),
reset_out6 => rxlink_rst_arr(i),
reset_out7 => rxframe_rst_arr(i)
);
rx_xcvr_ready_in_arr(i) <= rx_csr_lane_powerdown_arr(i) OR xcvr_rst_ctrl_rx_ready_arr(i);
-- Invert thr active-low resets
rx_avs_rst_n_arr(i) <= not rx_avs_rst_arr(i);
rxlink_rst_n_arr(i) <= not rxlink_rst_arr(i);
rxframe_rst_n_arr(i) <= not rxframe_rst_arr(i);
-----------------------------------------------------------------------------
......@@ -421,6 +428,7 @@ BEGIN
ELSE
rx_src_out_arr(i).data(15 downto 0) <= jesd204b_rx_link_data_arr(32*i+31 downto 32*i+16);
END IF;
f2_div1_cnt_arr(i) <= not f2_div1_cnt_arr(i);
END IF;
END IF;
END IF;
......@@ -457,7 +465,6 @@ BEGIN
PORT MAP (
clock => mm_clk,
reset => xcvr_rst_arr(0), -- From Reset Sequencer output1 as per example design
pll_powerdown => open, -- Todo: Check conduit. Which PLL?
rx_analogreset => rx_analogreset_arr, -- output to reset RX PMA. Release before deasserting link and avs resets (Intel JESD204B-UG p70)
rx_cal_busy => rx_cal_busy_arr, -- input from PHY
rx_digitalreset => rx_digitalreset_arr, -- output to reset RX PCS. Release before deasserting link and avs resets (Intel JESD204B-UG p70)
......
libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.ip
+ 255
− 61
View file @ 9c5728f8
......@@ -37,48 +37,6 @@
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>pll_powerdown</spirit:name>
<spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
<spirit:slave></spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>pll_powerdown</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>pll_powerdown</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
<spirit:displayName>associatedClock</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>associatedReset</spirit:name>
<spirit:displayName>associatedReset</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>prSafe</spirit:name>
<spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
<spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<altera:altera_assignments>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ui.blockdiagram.direction</spirit:name>
<spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
</spirit:parameter>
</spirit:parameters>
</altera:altera_assignments>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>reset</spirit:name>
<spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
......@@ -353,18 +311,6 @@
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>pll_powerdown</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>rx_analogreset</spirit:name>
<spirit:wire>
......@@ -494,7 +440,7 @@
<spirit:parameter>
<spirit:name>TX_PLL_ENABLE</spirit:name>
<spirit:displayName>Enable TX PLL reset control</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="TX_PLL_ENABLE">1</spirit:value>
<spirit:value spirit:format="long" spirit:id="TX_PLL_ENABLE">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>T_PLL_POWERDOWN</spirit:name>
......@@ -554,7 +500,7 @@
<spirit:parameter>
<spirit:name>RX_PER_CHANNEL</spirit:name>
<spirit:displayName>Use separate RX reset per channel</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="RX_PER_CHANNEL">0</spirit:value>
<spirit:value spirit:format="long" spirit:id="RX_PER_CHANNEL">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>gui_rx_auto_reset</spirit:name>
......@@ -574,7 +520,7 @@
<spirit:parameter>
<spirit:name>l_terminate_pll</spirit:name>
<spirit:displayName>l_terminate_pll</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="l_terminate_pll">0</spirit:value>
<spirit:value spirit:format="long" spirit:id="l_terminate_pll">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>l_terminate_tx</spirit:name>
......@@ -669,7 +615,257 @@
<spirit:parameter>
<spirit:name>lockedInterfaceDefinition</spirit:name>
<spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"></spirit:value>
<spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
<name>clock</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clock</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>reset</name>
<role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>rx_analogreset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>rx_analogreset</name>
<role>rx_analogreset</role>
<direction>Output</direction>
<width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>ui.blockdiagram.direction</key>
<value>output</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>rx_cal_busy</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>rx_cal_busy</name>
<role>rx_cal_busy</role>
<direction>Input</direction>
<width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>ui.blockdiagram.direction</key>
<value>input</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>rx_digitalreset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>rx_digitalreset</name>
<role>rx_digitalreset</role>
<direction>Output</direction>
<width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>ui.blockdiagram.direction</key>
<value>output</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>rx_is_lockedtodata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>rx_is_lockedtodata</name>
<role>rx_is_lockedtodata</role>
<direction>Input</direction>
<width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>ui.blockdiagram.direction</key>
<value>input</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>rx_ready</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>rx_ready</name>
<role>rx_ready</role>
<direction>Output</direction>
<width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>ui.blockdiagram.direction</key>
<value>output</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>systemInfos</spirit:name>
......@@ -685,9 +881,7 @@
<altera:port_mapping altera:name="clock" altera:internal="clock"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="pll_locked" altera:internal="xcvr_reset_control_0.pll_locked"></altera:interface_mapping>
<altera:interface_mapping altera:name="pll_powerdown" altera:internal="xcvr_reset_control_0.pll_powerdown" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="pll_powerdown" altera:internal="pll_powerdown"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="pll_powerdown" altera:internal="xcvr_reset_control_0.pll_powerdown"></altera:interface_mapping>
<altera:interface_mapping altera:name="pll_select" altera:internal="xcvr_reset_control_0.pll_select"></altera:interface_mapping>
<altera:interface_mapping altera:name="reset" altera:internal="xcvr_reset_control_0.reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="reset" altera:internal="reset"></altera:port_mapping>
......
libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.qsys
+ 11
− 58
View file @ 9c5728f8
......@@ -6,7 +6,7 @@
version="1.0"
description=""
tags=""
categories=""
categories="System"
tool="QsysPro" />
<parameter name="bonusData"><![CDATA[bonusData
{
......@@ -35,20 +35,7 @@
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos>
<entry>
<key>clk</key>
<value>
<connectionPointName>clk</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
<connPtSystemInfos/>
</systemInfosDefinition>]]></parameter>
<parameter name="systemScripts" value="" />
<parameter name="testBenchDutName" value="" />
......@@ -60,11 +47,7 @@
internal="xcvr_reset_control_0.clock"
type="clock"
dir="end" />
<interface
name="pll_powerdown"
internal="xcvr_reset_control_0.pll_powerdown"
type="conduit"
dir="end" />
<interface name="pll_powerdown" internal="xcvr_reset_control_0.pll_powerdown" />
<interface
name="reset"
internal="xcvr_reset_control_0.reset"
......@@ -136,43 +119,6 @@
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>pll_powerdown</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>pll_powerdown</name>
<role>pll_powerdown</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>ui.blockdiagram.direction</key>
<value>output</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>reset</name>
<type>reset</type>
......@@ -395,7 +341,14 @@
<displayName>Transceiver PHY Reset Controller Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors/>
<descriptors>
<descriptor>
<parameterDefaultValue>Stratix V</parameterDefaultValue>
<parameterName>device_family</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_FAMILY</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos/>
......
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