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RTSD
HDL
Commits
9bb01e16
Commit
9bb01e16
authored
2 years ago
by
Eric Kooistra
Browse files
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Use synthesis translate_off/on to avoid synthesis errors for REAL signals.
parent
e9512be7
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Pipeline
#34316
failed
2 years ago
Stage: simulation
Stage: synthesis
Stage: hardware
Changes
2
Pipelines
2
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2 changed files
libraries/dsp/st/src/vhdl/st_sst.vhd
+5
-2
5 additions, 2 deletions
libraries/dsp/st/src/vhdl/st_sst.vhd
libraries/dsp/st/src/vhdl/st_xsq.vhd
+6
-4
6 additions, 4 deletions
libraries/dsp/st/src/vhdl/st_xsq.vhd
with
11 additions
and
6 deletions
libraries/dsp/st/src/vhdl/st_sst.vhd
+
5
−
2
View file @
9bb01e16
...
...
@@ -21,7 +21,7 @@
LIBRARY
IEEE
,
common_lib
,
mm_lib
,
technology_lib
,
dp_lib
;
USE
IEEE
.
std_logic_1164
.
ALL
;
USE
IEEE
.
math_real
.
ALL
;
USE
IEEE
.
math_real
.
ALL
;
-- for sim only
USE
common_lib
.
common_pkg
.
ALL
;
USE
common_lib
.
common_mem_pkg
.
ALL
;
USE
common_lib
.
common_field_pkg
.
ALL
;
...
...
@@ -125,8 +125,9 @@ ARCHITECTURE str OF st_sst IS
SIGNAL
wrdata_re
:
STD_LOGIC_VECTOR
(
c_mem_data_w
-1
DOWNTO
0
);
SIGNAL
wrdata_im
:
STD_LOGIC_VECTOR
(
c_mem_data_w
-1
DOWNTO
0
);
SIGNAL
wrdata_power
:
REAL
;
-- Sim only signals for observing wrdata_power with indices in Wave window
SIGNAL
wrdata_power
:
REAL
;
SIGNAL
stat_bin
:
NATURAL
;
SIGNAL
stat_mosi
:
t_mem_mosi
:
=
c_mem_mosi_rst
;
...
...
@@ -243,10 +244,12 @@ BEGIN
wrdata_re
<=
RESIZE_MEM_UDATA
(
stat_data_re
)
WHEN
g_xst_enable
=
FALSE
ELSE
RESIZE_MEM_SDATA
(
stat_data_re
);
wrdata_im
<=
RESIZE_MEM_UDATA
(
stat_data_im
)
WHEN
g_xst_enable
=
FALSE
ELSE
RESIZE_MEM_SDATA
(
stat_data_im
);
-- synthesis translate_off
-- View SST or XST power values in wave window (stat_data_im = 0 for SST)
wrdata_power
<=
COMPLEX_RADIUS
(
TO_SREAL
(
stat_data_re
),
TO_SREAL
(
stat_data_im
))
**
2
.
0
;
stat_bin
<=
TO_UINT
(
stat_mosi
.
address
(
c_stat_ram
.
adr_w
-1
DOWNTO
0
))
/
g_stat_multiplex
;
-- synthesis translate_on
-- For SST or for real part of XST
stat_reg_re
:
ENTITY
common_lib
.
common_ram_crw_crw_ratio
...
...
This diff is collapsed.
Click to expand it.
libraries/dsp/st/src/vhdl/st_xsq.vhd
+
6
−
4
View file @
9bb01e16
...
...
@@ -46,7 +46,7 @@
LIBRARY
IEEE
,
common_lib
,
mm_lib
,
technology_lib
,
dp_lib
;
USE
IEEE
.
std_logic_1164
.
ALL
;
USE
IEEE
.
math_real
.
ALL
;
USE
IEEE
.
math_real
.
ALL
;
-- for sim only
USE
common_lib
.
common_pkg
.
ALL
;
USE
common_lib
.
common_mem_pkg
.
ALL
;
USE
common_lib
.
common_field_pkg
.
ALL
;
...
...
@@ -106,8 +106,9 @@ ARCHITECTURE str OF st_xsq IS
SIGNAL
wrdata_re
:
STD_LOGIC_VECTOR
(
c_mem_data_w
-1
DOWNTO
0
);
SIGNAL
wrdata_im
:
STD_LOGIC_VECTOR
(
c_mem_data_w
-1
DOWNTO
0
);
SIGNAL
wrdata_power
:
REAL
;
-- Sim only signals for observing wrdata_power with indices in Wave window
SIGNAL
wrdata_power
:
REAL
;
SIGNAL
stat_index
:
NATURAL
;
SIGNAL
a_sp
:
NATURAL
;
SIGNAL
b_sp
:
NATURAL
;
...
...
@@ -181,14 +182,15 @@ BEGIN
wrdata_re
<=
RESIZE_MEM_SDATA
(
stat_data_re
);
wrdata_im
<=
RESIZE_MEM_SDATA
(
stat_data_im
);
--
View XST power values in wave window
--
synthesis translate_off
wrdata_power
<=
COMPLEX_RADIUS
(
TO_SREAL
(
stat_data_re
),
TO_SREAL
(
stat_data_im
))
**
2
.
0
;
--
Translate
statistcs [crosslets][in A][in B]
order into indices
--
Indices for
statist
i
cs [crosslets][in A][in B]
stat_index
<=
TO_UINT
(
stat_mosi
.
address
(
c_stat_ram
.
adr_w
-1
DOWNTO
0
));
a_sp
<=
(
stat_index
/
g_nof_signal_inputs
)
MOD
g_nof_signal_inputs
;
b_sp
<=
stat_index
MOD
g_nof_signal_inputs
;
crosslet_index
<=
stat_index
/
c_xsq
;
-- synthesis translate_on
---------------------------------------------------------------
-- COMBINE MEMORY MAPPED INTERFACES
...
...
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