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Commit 9b3b7b41 authored by Eric Kooistra's avatar Eric Kooistra
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Used 'wait for 1 fs' to ease the usage of mmf_mm_bus_rd().

parent c9e787ee
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......@@ -148,6 +148,11 @@ PACKAGE mm_file_pkg IS
rd_addr : IN INTEGER; -- use integer to support full 32 bit range
SIGNAL rd_data : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL mm_clk : IN STD_LOGIC);
-- . rd_latency = 1
PROCEDURE mmf_mm_bus_rd(filename : IN STRING;
rd_addr : IN INTEGER;
SIGNAL rd_data : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL mm_clk : IN STD_LOGIC);
-- Procedure to get NOW via simulator status
PROCEDURE mmf_sim_get_now(filename : IN STRING; -- file name without extension
......@@ -481,6 +486,9 @@ PACKAGE BODY mm_file_pkg IS
hread(rd_line, v_rd_data);
file_close(stat_file);
rd_data <= v_rd_data;
-- wait to ensure rd_data has got v_rd_data, otherwise rd_data still holds the old data on procedure exit
-- the wait should be < mm_clk period/2 to not affect the read rate
WAIT FOR 1 fs;
ELSE
REPORT "mmf_mm_bus_rd() could not open " & stat_filename & " at " & time_to_str(now) SEVERITY FAILURE;
END IF;
......@@ -492,6 +500,15 @@ PACKAGE BODY mm_file_pkg IS
-- The END implicitely closes the files, if still necessary
END;
-- rd_latency = 1
PROCEDURE mmf_mm_bus_rd(filename : IN STRING;
rd_addr : IN INTEGER;
SIGNAL rd_data : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL mm_clk : IN STD_LOGIC) IS
BEGIN
mmf_mm_bus_rd(filename, 1, rd_addr, rd_data, mm_clk);
END;
PROCEDURE mmf_sim_get_now(filename : IN STRING; -- file name without extension
SIGNAL rd_now : OUT STRING;
SIGNAL mm_clk : IN STD_LOGIC) IS
......
......@@ -136,10 +136,7 @@ BEGIN
tb_state <= "Read ";
FOR I IN 0 TO c_mm_nof_dat-1 LOOP
mmf_mm_bus_rd(c_reg_r_w_dc_file_pathname, c_mem_reg.latency, I, file_rd_data, mm_clk);
IF I>0 THEN
-- skip first because it is undefined due to that assert needs to compare previous value
ASSERT I=TO_UINT(file_rd_data)+1 REPORT "Read data is wrong." SEVERITY ERROR;
END IF;
ASSERT I=TO_UINT(file_rd_data) REPORT "Read data is wrong." SEVERITY ERROR;
END LOOP;
-- Write/Read
......@@ -150,10 +147,7 @@ BEGIN
mmf_mm_bus_wr(c_reg_r_w_dc_file_pathname, v_addr, I, mm_clk);
proc_common_wait_some_cycles(mm_clk, c_cross_nof_mm_clk);
mmf_mm_bus_rd(c_reg_r_w_dc_file_pathname, c_mem_reg.latency, v_addr, file_rd_data, mm_clk);
IF I>0 THEN
-- skip first because it is undefined due to that assert needs to compare previous value
ASSERT TO_UINT(file_wr_data)=TO_UINT(file_rd_data)+1 REPORT "Write/read data is wrong." SEVERITY ERROR;
END IF;
ASSERT TO_UINT(file_wr_data)=TO_UINT(file_rd_data) REPORT "Write/read data is wrong." SEVERITY ERROR;
END LOOP;
proc_common_gen_pulse(mm_clk, get_now);
......
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