Added missing tb_mmp_st_histogram.vhd to sim reggression test.

libraries/dsp/st/hdllib.cfg

@@ -39,6 +39,7 @@ regression_test_vhdl =
     tb/vhdl/tb_tb_st_xsq.vhd
     tb/vhdl/tb_tb_st_xst.vhd
     #tb/vhdl/tb_st_calc.vhd   -- tb is not self checking yet
+    tb/vhdl/tb_mmp_st_histogram.vhd
     tb/vhdl/tb_tb_st_histogram.vhd