Skip to content
Snippets Groups Projects
Commit 97aa595c authored by Job van Wee's avatar Job van Wee
Browse files

Reading in whole bocks, Ready for review.

parent 031b3a6b
No related branches found
No related tags found
1 merge request!246Resolve L2SDP-706
Pipeline #29580 passed
...@@ -134,7 +134,6 @@ ARCHITECTURE rtl OF ddrctrl_controller IS ...@@ -134,7 +134,6 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
SIGNAL d_reg : t_reg := c_t_reg_init; SIGNAL d_reg : t_reg := c_t_reg_init;
SIGNAL q_reg : t_reg := c_t_reg_init; SIGNAL q_reg : t_reg := c_t_reg_init;
SIGNAL s_bim : NATURAL := g_bim;
BEGIN BEGIN
...@@ -175,6 +174,7 @@ BEGIN ...@@ -175,6 +174,7 @@ BEGIN
WHEN START_WRITING => WHEN START_WRITING =>
-- this state generates the first write burst.
IF TO_UINT(wr_fifo_usedw) > g_burstsize AND dvr_miso.done = '1' AND v.wr_burst_en = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN IF TO_UINT(wr_fifo_usedw) > g_burstsize AND dvr_miso.done = '1' AND v.wr_burst_en = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN
v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC(TO_UINT(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0))+q_reg.stop_burstsize, c_adr_w); v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC(TO_UINT(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0))+q_reg.stop_burstsize, c_adr_w);
v.dvr_mosi.wr := '1'; v.dvr_mosi.wr := '1';
...@@ -191,8 +191,7 @@ BEGIN ...@@ -191,8 +191,7 @@ BEGIN
WHEN WRITING => WHEN WRITING =>
-- if adr mod g_burstsize = 0 -- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
-- this makes sure that only ones every 64 writes a writeburst is started.
IF TO_UINT(wr_fifo_usedw) > g_burstsize AND dvr_miso.done = '1' AND q_reg.wr_burst_en = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN IF TO_UINT(wr_fifo_usedw) > g_burstsize AND dvr_miso.done = '1' AND q_reg.wr_burst_en = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN
v.dvr_mosi.burstbegin := '1'; v.dvr_mosi.burstbegin := '1';
v.wr_burst_en := '0'; v.wr_burst_en := '0';
...@@ -228,7 +227,7 @@ BEGIN ...@@ -228,7 +227,7 @@ BEGIN
WHEN SET_STOP => WHEN SET_STOP =>
--setting a stop address dependend on the g_stop_percentage -- this state sets a stop address dependend on the g_stop_percentage.
IF inp_adr+c_pof_ma >= g_max_adr THEN IF inp_adr+c_pof_ma >= g_max_adr THEN
v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr-c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO 0); v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr-c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO 0);
ELSE ELSE
...@@ -271,9 +270,11 @@ BEGIN ...@@ -271,9 +270,11 @@ BEGIN
WHEN STOP_WRITING => WHEN STOP_WRITING =>
-- this state stops the writing by generatign one last whole write burst which almost empties wr_fifo.
v.wr_sosi.valid := '0'; v.wr_sosi.valid := '0';
v.dvr_mosi.burstbegin := '0'; v.dvr_mosi.burstbegin := '0';
v.stopped := '1'; v.stopped := '1';
v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
-- wait until the write burst is finished -- wait until the write burst is finished
IF inp_data_stopped = '0' THEN IF inp_data_stopped = '0' THEN
v.state := STOP_WRITING; v.state := STOP_WRITING;
...@@ -309,7 +310,7 @@ BEGIN ...@@ -309,7 +310,7 @@ BEGIN
WHEN LAST_WRITE_BURST => WHEN LAST_WRITE_BURST =>
-- this state stops the writing by generatign one last write burst which empties wr_fifo.
IF dvr_miso.done = '1' THEN IF dvr_miso.done = '1' THEN
v.dvr_mosi.burstbegin := '1'; v.dvr_mosi.burstbegin := '1';
v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0); v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0);
...@@ -326,17 +327,18 @@ BEGIN ...@@ -326,17 +327,18 @@ BEGIN
WHEN START_READING => WHEN START_READING =>
-- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
v.dvr_mosi.burstbegin := '0'; v.dvr_mosi.burstbegin := '0';
v.outp_bsn := TO_UVEC(TO_UINT(inp_sosi.bsn)-g_bim, c_dp_stream_bsn_w); v.outp_bsn := TO_UVEC(TO_UINT(inp_sosi.bsn)-g_bim, c_dp_stream_bsn_w);
IF dvr_miso.done = '1' AND v.rd_burst_en = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN IF dvr_miso.done = '1' AND v.rd_burst_en = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN
v.dvr_mosi.burstbegin := '1'; v.dvr_mosi.burstbegin := '1';
v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := TO_UVEC(g_burstsize-q_reg.stop_burstsize, dvr_mosi.burstsize'length); v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := TO_UVEC(g_burstsize-q_reg.stop_burstsize, dvr_mosi.burstsize'length);
v.dvr_mosi.wr := '0'; v.dvr_mosi.wr := '0';
v.dvr_mosi.rd := '1'; v.dvr_mosi.rd := '1';
v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC(TO_UINT(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0))+q_reg.stop_burstsize, c_adr_w); v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC(TO_UINT(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0))+q_reg.stop_burstsize, c_adr_w);
v.rd_burst_en := '0'; v.rd_burst_en := '0';
v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0))+g_burstsize; v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0))+g_burstsize;
END IF; END IF;
-- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another. -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
...@@ -383,7 +385,7 @@ BEGIN ...@@ -383,7 +385,7 @@ BEGIN
WHEN STOP_READING => WHEN STOP_READING =>
-- this is the last read burst, this make sure every data containing word in the memory has been read.
IF TO_UINT(rd_fifo_usedw) <= g_burstsize AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' THEN IF TO_UINT(rd_fifo_usedw) <= g_burstsize AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' THEN
v.dvr_mosi.burstbegin := '1'; v.dvr_mosi.burstbegin := '1';
v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0); v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0);
...@@ -426,8 +428,6 @@ BEGIN ...@@ -426,8 +428,6 @@ BEGIN
v.state := SET_STOP; v.state := SET_STOP;
ELSIF q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND q_reg.stopped = '0' THEN ELSIF q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND q_reg.stopped = '0' THEN
v.state := STOP_WRITING; v.state := STOP_WRITING;
--ELSIF v.stopped = '0' AND inp_sosi.sop = '1' AND q_reg.started = '1' THEN
--v.state := START_WRITING;
ELSIF v.stopped = '0' AND inp_sosi.valid = '1' AND q_reg.started = '1' THEN ELSIF v.stopped = '0' AND inp_sosi.valid = '1' AND q_reg.started = '1' THEN
v.state := WRITING; v.state := WRITING;
ELSIF q_reg.stopped = '1' THEN ELSIF q_reg.stopped = '1' THEN
......
...@@ -212,7 +212,7 @@ BEGIN ...@@ -212,7 +212,7 @@ BEGIN
WHEN FIRST_READ => WHEN FIRST_READ =>
-- fills the first half of c_v and generates a output from it. -- fills the first half of c_v and generates output from it.
v.out_ready := '0'; v.out_ready := '0';
v.c_v(c_v_w-1 DOWNTO 0) := (OTHERS => '0'); v.c_v(c_v_w-1 DOWNTO 0) := (OTHERS => '0');
v.c_v(g_in_data_w-1 DOWNTO 0) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0); v.c_v(g_in_data_w-1 DOWNTO 0) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
...@@ -240,8 +240,8 @@ BEGIN ...@@ -240,8 +240,8 @@ BEGIN
v.state := READING; v.state := READING;
WHEN BSN => WHEN BSN =>
-- generating output data from c_v but past the halfway point of c_v so there needs to be new data added also increases the bsn output
v.out_sosi.valid := '0'; v.out_sosi.valid := '0';
-- generating output data from c_v but past the halfway point of c_v so there needs to be new data added
IF q_reg.dd_fresh = '1' AND q_reg.valid_data = '1' THEN IF q_reg.dd_fresh = '1' AND q_reg.valid_data = '1' THEN
-- generate output from the middle of c_v -- generate output from the middle of c_v
v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := q_reg.c_v((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of); v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := q_reg.c_v((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
......
...@@ -179,7 +179,7 @@ BEGIN ...@@ -179,7 +179,7 @@ BEGIN
-- wr fifo has delay of 4 clockcylces after reset -- wr fifo has delay of 4 clockcylces after reset
-- filling the input data vectors with the corresponding numbers -- filling the input data vectors with the corresponding numbers
run_multiple_times : FOR K in 0 TO 2 LOOP run_multiple_times : FOR K in 0 TO 3 LOOP
make_data : FOR J IN 0 TO c_bim*g_block_size-1 LOOP make_data : FOR J IN 0 TO c_bim*g_block_size-1 LOOP
in_data_cnt <= in_data_cnt+1; in_data_cnt <= in_data_cnt+1;
fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment