-Replaced mixed width FIFO (64b->32b) with dp_fifo_sc + dp_rapack_data so

 the BSN and channel are forwarded properly to the visibility offload.

applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd

@@ -323,7 +323,9 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
   SIGNAL correlator_src_out_arr                      : t_dp_sosi_arr(1-1 DOWNTO 0);
   
   -- 1GbE Visibility Offload
-  SIGNAL dp_fifo_dc_mixed_widths_snk_in              : t_dp_sosi;
+  SIGNAL dp_fifo_sc_snk_in              : t_dp_sosi;
+  SIGNAL dp_repack_data_snk_in                       : t_dp_sosi;
+  SIGNAL dp_repack_data_snk_out                      : t_dp_siso;
   SIGNAL apertif_unb1_correlator_vis_offload_snk_in  : t_dp_sosi;
   SIGNAL apertif_unb1_correlator_vis_offload_snk_out : t_dp_siso;
   SIGNAL dp_offload_tx_src_out_arr                   : t_dp_sosi_arr(1-1 DOWNTO 0);
@@ -989,28 +991,47 @@ BEGIN
   gen_wires_complex : IF g_sim=FALSE or g_sim_fast=FALSE GENERATE
     p_wires_complex : PROCESS(correlator_src_out_arr)
     BEGIN
-      dp_fifo_dc_mixed_widths_snk_in <= correlator_src_out_arr(0);
-      dp_fifo_dc_mixed_widths_snk_in.data(64-1 DOWNTO 0) <= correlator_src_out_arr(0).re(64/2-1 DOWNTO 0) & correlator_src_out_arr(0).im(64/2-1 DOWNTO 0);
+      dp_fifo_sc_snk_in <= correlator_src_out_arr(0);
+      dp_fifo_sc_snk_in.data(64-1 DOWNTO 0) <= correlator_src_out_arr(0).re(64/2-1 DOWNTO 0) & correlator_src_out_arr(0).im(64/2-1 DOWNTO 0);
     END PROCESS;
   END GENERATE;
 
   -----------------------------------------------------------------------------
   -- 64b -> 32b 
   -----------------------------------------------------------------------------
-  u_dp_fifo_dc_mixed_widths : ENTITY dp_lib.dp_fifo_dc_mixed_widths
+  u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
   GENERIC MAP (
-    g_wr_data_w    => 64,
-    g_rd_data_w    => 32,
+    g_data_w         => 64, 
     g_use_ctrl       => TRUE,
-    g_wr_fifo_size => 300
+    g_use_bsn        => TRUE,
+    g_use_channel    => TRUE,
+    g_bsn_w          => 64,
+    g_channel_w      => 16,
+    g_fifo_size      => 300 + 20
   )
   PORT MAP (
-    wr_rst         => dp_rst,
-    wr_clk         => dp_clk,
-    rd_rst         => dp_rst,
-    rd_clk         => dp_clk,
+    rst         => dp_rst,
+    clk         => dp_clk,
+  
+    snk_in      => dp_fifo_sc_snk_in,
+
+    src_in      => dp_repack_data_snk_out,
+    src_out     => dp_repack_data_snk_in
+  );
+
+  u_dp_repack_data : ENTITY dp_lib.dp_repack_data
+  GENERIC MAP (
+    g_in_dat_w      => 64,
+    g_in_nof_words  => 1,
+    g_out_dat_w     => 32,
+    g_out_nof_words => 2
+  )
+  PORT MAP (
+    rst            => dp_rst,
+    clk            => dp_clk,
 
-    snk_in         => dp_fifo_dc_mixed_widths_snk_in,
+    snk_out        => dp_repack_data_snk_out,
+    snk_in         => dp_repack_data_snk_in,
                    
     src_in         => apertif_unb1_correlator_vis_offload_snk_out,
     src_out        => apertif_unb1_correlator_vis_offload_snk_in

applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator_vis_offload.vhd

@@ -188,6 +188,7 @@ BEGIN
     hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_dst_port"       ) DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port"      )) <= x"D0" & ID;
     hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_src_addr"        ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr"       )) <= x"0A63" & id_backplane & INCR_UVEC(id_chip, 1);
 
+    hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_channel_index"   ) DOWNTO field_lo(c_hdr_field_arr, "id_channel_index"  )) <= snk_in.channel(15 DOWNTO 0);
     hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_timestamp"       ) DOWNTO field_lo(c_hdr_field_arr, "id_timestamp"      )) <= snk_in.bsn;
   END GENERATE;