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Commit 96c2dcb8 authored by Pepping's avatar Pepping
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Initial commit of mmm autogeneration scripts. Still comments to be added.

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tools/oneclick/base/entity.py 0 → 100644
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View file @ 96c2dcb8
###############################################################################
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
"""
"""
import common as cm
import common_dict_file
import sys
import os
import os.path
import shutil
dirList = ["IN", "in", "OUT", "out", "INOUT", "inout"]
class Port:
def __init__(self, name, dir, type, default=""):
self.name = name
if dir in dirList:
self.dir = dir
else:
print """Not a valid dir type. Should be "IN", "OUT" or "INOUT" """
self.type = type
self.default = default
def setPortDir(self, newDir):
self.dir = newDir
class Generic:
def __init__(self, name, type, default=""):
self.name = name
self.type = type
self.default = default
def setPortDir(self, newDir):
self.dir = newDir
class Entity:
s_port_start = " PORT (\n"
s_port_map_start = " PORT MAP(\n"
s_generic_start = " GENERIC (\n"
def __init__(self, name = ""):
"""
"""
self.name = name
self.generics = []
self.ports = []
self.portNames = []
self.longestPortName = 15
self.longestPortDir = 3
self.genericNames = []
self.genericTypes = []
self.longestGenericName = 15
self.longestGenericType = 8
def read_entity_from_file(self, path, name):
f = file((path + name + ".vhd"), "r")
s = ""
s = f.readline()
# Read the entity name
while not(('ENTITY ' in s) or ('entity ' in s)):
s = f.readline()
self.name = s.split(" ")[1]
s = f.readline()
# Find the start of the generic definitions
if('generic' in s) or ('GENERIC' in s):
while not(');') in s:
s = f.readline()
if not(self.comment_or_empty(s)):
if ');' in s:
s = f.readline()
break
s = self.remove_added_comment(s)
s_comp = s.split(": ")
newGenericName = s_comp[0].strip()
# Check if a default value is assigned
if(":=" in s_comp[1]):
s_comp1 = s_comp[1].split(":=")
newGenericDefault = (s_comp1[1].strip(";")).strip()
s_type = s_comp1[0]
else:
newGenericDefault = ""
s_type = s_comp[1]
newGenericType = (s_type.strip(";")).strip()
newGeneric = Generic(newGenericName, newGenericType, newGenericDefault)
self.generics.append(newGeneric)
if('port' in s) or ('PORT' in s):
while not('end entity ') in s:
s = f.readline()
if not(self.comment_or_empty(s)):
if s.strip() == ');':
break
s = self.remove_added_comment(s)
s_comp = s.split(": ")
newPortName = s_comp[0].strip()
# Check if a default value is assigned
if(":=" in s_comp[1]):
s_comp1 = s_comp[1].split(":=")
newPortDefault = (s_comp1[1].strip(";")).strip()
s_dir_type = s_comp1[0]
else:
newPortDefault = ""
s_dir_type = s_comp[1]
newPortDir = s_dir_type.split(" ", 1)[0]
newPortType = ((s_dir_type.split(" ", 1)[1]).strip(";")).strip()
self.add_port(newPortName, newPortDir, newPortType, newPortDefault)
f.close()
def comment_or_empty(self, s):
s_strip = s.strip()
return (s_strip.startswith("--") or not(s.strip()))
def remove_added_comment(self, s):
i = s.find('--')
if i != -1:
s = s[0:i] + "\n"
return s.strip()
def make_instance(self, inst_type="ENTITY"):
if self.generics:
self.set_longest_generic_name()
self.set_longest_generic_type()
if self.ports:
self.set_longest_port_name()
self.set_longest_port_dir()
# Create start
s_return = inst_type + " " + self.name +" IS\n"
for i in range(len(self.generics)):
if(i == 0):
s_return = s_return + self.s_generic_start
s_generic = " " + self.generics[i].name.ljust(self.longestGenericName) + " : " + self.generics[i].type.ljust(self.longestGenericType)
if(self.generics[i].default != ""):
s_generic = s_generic + " := " + self.generics[i].default
if(i != len(self.generics)-1):
s_generic = s_generic + ";\n"
else:
s_generic = s_generic + "\n );\n"
s_return = s_return + s_generic
for i in range(len(self.ports)):
if(i == 0):
s_return = s_return + self.s_port_start
s_port = " " + self.ports[i].name.ljust(self.longestPortName) + " : " + self.ports[i].dir.ljust(self.longestPortDir) + " " + self.ports[i].type
if(self.ports[i].default != ""):
s_port = s_port + " := " + self.ports[i].default
if(i != len(self.ports)-1):
s_port = s_port + ";\n"
else:
s_port = s_port + "\n );\n"
s_return = s_return + s_port
s_return = s_return + "END " + inst_type + " " + self.name + ";\n\n"
return s_return
def make_entity_instance(self, indend = 0):
return self.apply_indend(self.make_instance("ENTITY"), indend)
def make_component_instance(self, indend = 0):
return self.apply_indend(self.make_instance("COMPONENT"), indend)
def apply_indend(self, s, indend):
s_indend = ""
for i in range(indend):
s_indend = s_indend + " "
s_return =s_indend + s.replace('\n', '\n' + s_indend)
return (s_return)
def set_longest_port_name(self):
self.portNames = []
for i in range(len(self.ports)):
self.portNames.append(self.ports[i].name)
self.longestPortName = len(max(self.portNames, key=len))
def set_longest_port_dir(self):
self.longestPortDir = 0
for i in range(len(self.ports)):
if(len(self.ports[i].dir) > self.longestPortDir):
self.longestPortDir = len(self.ports[i].dir)
def set_longest_generic_name(self):
self.genericNames = []
for i in range(len(self.generics)):
self.genericNames.append(self.generics[i].name)
self.longestGenericName = len(max(self.genericNames, key=len))
def set_longest_generic_type(self):
self.genericTypes = []
for i in range(len(self.generics)):
self.genericTypes.append(self.generics[i].type)
self.longestGenericType = len(max(self.genericTypes, key=len))
def add_port(self, name, dir, type, default = ""):
newPort = Port(name, dir, type, default)
self.ports.append(newPort)
tools/oneclick/base/mmm_gen.py 0 → 100644
+ 447
− 0
View file @ 96c2dcb8
###############################################################################
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
"""
"""
import common as cm
import common_dict_file
import sys
import os
import os.path
import shutil
import entity
s_header = """--------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
"""
s_libraries = """LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
"""
s_signals_clk = "SIGNAL i_mm_clk : STD_LOGIC := '1';\n\
SIGNAL i_dp_clk : STD_LOGIC := '1';\n"
s_connect_mm_clk = "mm_clk <= i_mm_clk;\n"
s_connect_dp_clk = "dp_clk <= i_dp_clk;\n"
s_fileio_start = "----------------------------------------------------------------------------\n\
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.\n\
----------------------------------------------------------------------------\n\
gen_mm_file_io : IF g_sim = TRUE GENERATE\n"
s_fileio_mm_clk = "mm_locked <= '0', '1' AFTER c_mm_clk_period*5;\n\
i_mm_clk <= NOT i_mm_clk AFTER c_mm_clk_period/2;\n"
s_fileio_dp_clk = "i_dp_clk <= NOT i_dp_clk AFTER c_dp_clk_period/2;\n"
s_fileio_poll = "----------------------------------------------------------------------------\n\
-- Procedure that polls a sim control file that can be used to e.g. get\n\
-- the simulation time in ns\n\
----------------------------------------------------------------------------\n\
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & \"sim.ctrl\", c_mmf_unb_file_path & \"sim.stat\");\n"
s_end_generate = "\nEND GENERATE;"
s_master_header = "----------------------------------------------------------------------------\n\
-- SOPC or QSYS for synthesis\n\
----------------------------------------------------------------------------\n"
s_arch_begin = "\nBEGIN\n\n"
s_arch_end = "\nEND str;\n"
peripherals_vhdl2python = { 'reg_wdi' : "reg_wdi",\
'reg_unb_system_info' : "pio_system_info",\
'rom_unb_system_info' : "rom_system_info",\
'reg_unb_sens' : "reg_unb_sens",\
'reg_ppsh' : "pio_pps",\
'reg_eth' : "avs_eth_0_mms_reg"}
class QsysEntity(entity.Entity):
def make_qsys_instance(self, peripherals):
s_start = "u_" + self.name + " : " + self.name + "\n" + self.s_port_map_start
self.portNames.sort()
s_port_connects = ""
for s in self.portNames:
s_connect = ""
if "_address_export" in s:
s_reg_name = self.name_convert(s.split("_address_export")[0])
if s_reg_name[-1].isdigit():
s_index = s_reg_name.rsplit("_", 1)[1]
s_reg_name = s_reg_name.rsplit("_", 1)[0]
s_connect = s_reg_name + "_mosi_arr(" + s_index + ").address("
else:
s_connect = s_reg_name + "_mosi.address("
span = self.find_span(s_reg_name, peripherals)
if span == 1:
s_connect = s_connect + "0),"
else:
s_connect = s_connect + str(span-1) + " DOWNTO 0),"
if "_read_export" in s:
s_reg_name = self.name_convert(s.split("_read_export")[0])
if s_reg_name[-1].isdigit():
s_index = s_reg_name.rsplit("_", 1)[1]
s_reg_name = s_reg_name.rsplit("_", 1)[0]
s_connect = s_reg_name + "_mosi_arr(" + s_index + ").rd,"
else:
s_connect = s_reg_name + "_mosi.rd,"
if "_write_export" in s:
s_reg_name = self.name_convert(s.split("_write_export")[0])
if s_reg_name[-1].isdigit():
s_index = s_reg_name.rsplit("_", 1)[1]
s_reg_name = s_reg_name.rsplit("_", 1)[0]
s_connect = s_reg_name + "_mosi_arr(" + s_index + ").wr,"
else:
s_connect = s_reg_name + "_mosi.wr,"
if "_readdata_export" in s:
s_reg_name = self.name_convert(s.split("_readdata_export")[0])
if s_reg_name[-1].isdigit():
s_index = s_reg_name.rsplit("_", 1)[1]
s_reg_name = s_reg_name.rsplit("_", 1)[0]
s_connect = s_reg_name + "_mosi_arr(" + s_index + ").rddata(c_word_w-1 DOWNTO 0),"
else:
s_connect = s_reg_name + "_mosi.rddata(c_word_w-1 DOWNTO 0),"
if "_writedata_export" in s:
s_reg_name = self.name_convert(s.split("_writedata_export")[0])
if s_reg_name[-1].isdigit():
s_index = s_reg_name.rsplit("_", 1)[1]
s_reg_name = s_reg_name.rsplit("_", 1)[0]
s_connect = s_reg_name + "_mosi_arr(" + s_index + ").wrdata(c_word_w-1 DOWNTO 0),"
else:
s_connect = s_reg_name + "_mosi.wrdata(c_word_w-1 DOWNTO 0),"
if "_clk_export" in s:
s_connect = "OPEN,"
if "_reset_export" in s:
s_connect = "OPEN,"
# Exceptions for the ethernet
if "tse_clk" in s:
s_connect = "eth1g_tse_clk,"
if "eth1g_mm_rst_export" in s:
s_connect = "eth1g_mm_rst,"
if "eth1g_irq_export" in s:
s_connect = "eth1g_reg_interrupt,"
if "eth1g_tse_waitrequest_export" in s:
s_connect = "eth1g_tse_miso.waitrequest,"
# Exceptions for the debug_wave
if "out_port_from_the_pio_debug_wave" in s:
s_connect = "OPEN,"
# Exceptions for the debug_wave
if "out_port_from_the_pio_wdi" in s:
s_connect = "pout_wdi,"
# mm_clk + PLL's
if "mm_clk" in s:
s_connect = "i_mm_clk,"
if "epcs_clk" in s:
s_connect = "OPEN,"
if s == "reset_n":
s_connect = "xo_rst_n,"
if "altpll_0_locked_export" in s:
s_connect = "mm_locked,"
if "altpll_1_locked_export" in s:
s_connect = "OPEN,"
if "altpll_1_c0_clk" in s:
s_connect = "i_dp_clk,"
if "_areset_export" in s:
s_connect = "xo_rst,"
if "_phasedone_export" in s:
s_connect = "OPEN,"
if "clk_0" in s:
s_connect = "xo_clk,"
if "board_clk_clk" in s:
s_connect = "board_clk,"
if "board_reset_reset" in s:
s_connect = "board_reset_n,"
if "altpll_0_c3_clk" in s:
s_connect = "OPEN,"
s_port_connects = s_port_connects + " " + s.ljust(self.longestPortName) + " => " + s_connect + "\n"
s_port_connects = s_port_connects.rsplit(",",1)[0] + "\n"
return s_start + s_port_connects + ");"
def name_convert(self, name):
new_name = name
for reg_name, sopc_name in peripherals_vhdl2python.items():
if sopc_name == name:
new_name = reg_name
return new_name
def find_span(self, name, peripherals):
span = 0
for i in range(len(peripherals)):
if peripherals[i][0] == name:
span = int(peripherals[i][2])
return span
class MmmGenerate:
def __init__(self, mmmDir, mmmFileName='mmm.cfg'):
"""
"""
self.mmmDir = mmmDir
self.mmmFileName = mmmFileName
# mmm config files
self.mmm = common_dict_file.CommonDictFile(mmmDir, mmmFileName) # library dict files
if self.mmm.nof_dicts==0: sys.exit('Error : No mmm config file found')
# Keep list of HDL library names
self.mmm_name = "mmm_" + self.mmm.get_key_values('mmm_name')
self.VhdlFileName = self.mmm_name + '.vhd'
self.input_clks = self.mmm.get_key_values('input_clks')
self.output_clks = self.mmm.get_key_values('output_clks')
self.unb1_board_peripherals_temp = self.mmm.get_key_values('unb1_board_peripherals').split()
self.unb1_board_peripherals = self.chunks(self.unb1_board_peripherals_temp, 3)
self.custom_peripherals_temp = self.mmm.get_key_values('custom_peripherals').split()
self.custom_peripherals = self.chunks(self.custom_peripherals_temp, 3)
self.peripherals = self.unb1_board_peripherals + self.custom_peripherals
self.mm_clk_period = self.mmm.get_key_values('sim_mm_clk_period')
self.dp_clk_period = self.mmm.get_key_values('sim_dp_clk_period')
self.QsysName = "qsys_" + self.mmm.get_key_values('mmm_name')
self.QsysFileName = self.QsysName + '.vhd'
def chunks(self, l, n):
n = max(1, n)
return [l[i:i + n] for i in range(0, len(l), n)]
def make_mm_port_map_string(self, peripheral):
print peripheral
if(int(peripheral[1]) == 1):
port_mosi = "\n" + peripheral[0] + "_mosi : OUT t_mem_mosi;\n"
port_miso = "" + peripheral[0] + "_miso : IN t_mem_miso;\n"
port_string = port_mosi + port_miso
elif(int(peripheral[1]) > 1):
port_mosi = "\n" + peripheral[0] + "_mosi_arr : OUT t_mem_mosi_arr(" + str(int(peripheral[1])-1) + " DOWNTO 0);\n"
port_miso = "" + peripheral[0] + "_miso_arr : IN t_mem_miso_arr(" + str(int(peripheral[1])-1) + " DOWNTO 0);\n"
port_string = port_mosi + port_miso
return port_string
def make_mm_file_io_entry(self, peripheral):
if peripheral[0] in peripherals_vhdl2python:
python_name = peripherals_vhdl2python[peripheral[0]].upper()
else:
python_name = peripheral[0].upper()
file_io_entry = ""
if(int(peripheral[1]) == 1):
file_io_entry = "u_mm_file_" + peripheral[0] + " : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & " + r'"' + python_name + r'"' + ")\n PORT MAP(mm_rst, i_mm_clk, " + peripheral[0] + "_mosi, " + peripheral[0] + "_miso );\n"
return file_io_entry
def read_entity_from_file(self, path, name):
f = file((path + name + ".vhd"), "r")
s_return = ""
s = ""
while not('entity ' + name) in s:
s = f.readline()
s_return = s_return + s
while not('end entity') in s:
s = f.readline()
# remove comments
i = s.find('--')
if i != -1:
s=s[0:i] + "\n"
s_return = s_return + s
f.close()
return s_return
if __name__ == '__main__':
mmmDir = '../../../applications/apertif/designs/apertif_unb1_correlator/src/python/'
buildDir = '../../../build/quartus/apertif_unb1_correlator/qsys_apertif_unb1_correlator/simulation/'
mm_dir = '../../../../../UniBoard/trunk/Firmware/modules/mm/tb/vhdl/'
mm_file = "mm_file"
mmmFileName = 'mmm.cfg'
mmm_conf = MmmGenerate( mmmDir = mmmDir, mmmFileName=mmmFileName)
###################################
# Define the entity definitions
###################################
ent_qsys = QsysEntity()
ent_mmm = entity.Entity(name = mmm_conf.mmm_name)
ent_mm_file = entity.Entity()
###################################
# Read the Qsys entity definition
###################################
ent_qsys.read_entity_from_file(buildDir, mmm_conf.QsysName)
s_qsys_comp = ent_qsys.make_component_instance(indend = 0)
###################################
# Read the mm_file entity definition
###################################
ent_mm_file.read_entity_from_file(mm_dir, mm_file)
s_mm_file_comp = ent_mm_file.make_component_instance(indend = 0)
###################################
# Make the entity definition
###################################
# Start with entity header
s_arch_content = ""
s_arch_file = ""
# Add input clks
if "xo_clk" in mmm_conf.input_clks:
ent_mmm.add_port("xo_clk", "IN", "STD_LOGIC", "1")
ent_mmm.add_port("xo_rst_n", "IN", "STD_LOGIC", "0")
ent_mmm.add_port("xo_rst", "IN", "STD_LOGIC", "0")
if "board_clk" in mmm_conf.input_clks:
ent_mmm.add_port("board_clk", "IN", "STD_LOGIC", "1")
ent_mmm.add_port("board_reset_n", "IN", "STD_LOGIC", "1")
# Add output clks
if "mm_clk" in mmm_conf.output_clks:
ent_mmm.add_port("mm_clk", "OUT", "STD_LOGIC")
ent_mmm.add_port("mm_rst", "IN" , "STD_LOGIC", "1")
ent_mmm.add_port("mm_locked", "OUT", "STD_LOGIC" )
s_arch_content = s_arch_content + s_connect_mm_clk
s_arch_file = s_arch_file + s_fileio_mm_clk
if "dp_clk" in mmm_conf.output_clks:
ent_mmm.add_port("dp_clk", "OUT", "STD_LOGIC", "1")
s_arch_content = s_arch_content + s_connect_dp_clk
s_arch_file = s_arch_file + s_fileio_dp_clk
# Add UNB1 board peripherals
# 1GbE control interface always:
ent_mmm.add_port("eth1g_tse_clk", "OUT", "STD_LOGIC")
ent_mmm.add_port("eth1g_mm_rst", "OUT", "STD_LOGIC")
ent_mmm.add_port("eth1g_tse_mosi", "OUT", "t_mem_mosi")
ent_mmm.add_port("eth1g_tse_miso", "IN" , "t_mem_miso", "c_mem_miso_rst")
ent_mmm.add_port("eth1g_reg_mosi", "OUT", "t_mem_mosi")
ent_mmm.add_port("eth1g_reg_miso", "IN" , "t_mem_miso", "c_mem_miso_rst")
ent_mmm.add_port("eth1g_reg_interrupt", "IN", "STD_LOGIC")
ent_mmm.add_port("eth1g_ram_mosi", "OUT", "t_mem_mosi")
ent_mmm.add_port("eth1g_ram_miso", "IN", "t_mem_miso", "c_mem_miso_rst")
for s in mmm_conf.unb1_board_peripherals:
if(int(s[1]) == 1):
ent_mmm.add_port(s[0] + "_mosi", "OUT", "t_mem_mosi")
ent_mmm.add_port(s[0] + "_miso", "IN", "t_mem_miso", "c_mem_miso_rst")
elif(int(s[1]) > 1):
ent_mmm.add_port(s[0] + "_mosi_arr", "OUT", "t_mem_mosi_arr(" + str(int(s[1])-1) + " DOWNTO 0)")
ent_mmm.add_port(s[0] + "_miso_arr", "IN", "t_mem_miso_arr(" + str(int(s[1])-1) + " DOWNTO 0)", "(others => c_mem_miso_rst)")
s_arch_file = s_arch_file + mmm_conf.make_mm_file_io_entry(s)
# Add reg_wdi port if included
if "reg_wdi" in mmm_conf.unb1_board_peripherals:
ent_mmm.add_port("pout_wdi", "OUT", "STD_LOGIC", "1")
# Add custom peripherals
for s in mmm_conf.custom_peripherals:
if(int(s[1]) == 1):
ent_mmm.add_port(s[0] + "_mosi", "OUT", "t_mem_mosi")
ent_mmm.add_port(s[0] + "_miso", "IN", "t_mem_miso", "c_mem_miso_rst")
elif(int(s[1]) > 1):
ent_mmm.add_port(s[0] + "_mosi_arr", "OUT", "t_mem_mosi_arr(" + str(int(s[1])-1) + " DOWNTO 0)")
ent_mmm.add_port(s[0] + "_miso_arr", "IN", "t_mem_miso_arr(" + str(int(s[1])-1) + " DOWNTO 0)", "(others => c_mem_miso_rst)")
s_arch_file = s_arch_file + mmm_conf.make_mm_file_io_entry(s)
s_entity = ent_mmm.make_entity_instance()
###################################
# Make the architecture header
###################################
s_arch_start = "ARCHITECTURE str OF "+ str(mmm_conf.mmm_name) + " IS\n\n"
s_arch_constants = ""
s_arch_constants = s_arch_constants + "CONSTANT c_mm_clk_period : TIME := " + str(mmm_conf.mm_clk_period) + " ns;\n"
s_arch_constants = s_arch_constants + "CONSTANT c_dp_clk_period : TIME := " + str(mmm_conf.dp_clk_period) + " ns;\n"
s_arch_constants = s_arch_constants + "CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, " + r'"FN", "BN"' + ");\n"
s_arch_constants = s_arch_constants + "CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type=" + r'"BN"' +", g_sim_node_nr-4, g_sim_node_nr);\n"
s_arch_components = s_mm_file_comp + s_qsys_comp
s_arch_header = s_arch_start + ent_qsys.apply_indend(s_arch_constants + "\n" + s_arch_components + s_signals_clk, 2)
###################################
# Make the architecture content
###################################
# Make File I/O master
eth_peripheral = ['reg_eth', '1', '8']
s_arch_file = s_arch_file + mmm_conf.make_mm_file_io_entry(eth_peripheral)
s_file = s_fileio_start + ent_qsys.apply_indend(s_arch_file + s_fileio_poll, 2) + s_end_generate + "\n"
# Make QSYS master
s_master_start = s_master_header + "gen_" + ent_qsys.name + " : IF g_sim = FALSE GENERATE\n"
s_master = s_master_start + ent_qsys.apply_indend(ent_qsys.make_qsys_instance(mmm_conf.peripherals), 2) + s_end_generate + "\n"
s_arch_total = s_arch_begin + ent_qsys.apply_indend(s_arch_content + s_file + s_master, 2) + s_arch_end
string_elements = [s_header, s_libraries, s_entity, s_arch_header, s_arch_total ]
###################################
# Write the whole string to a file
###################################
f = file(mmm_conf.VhdlFileName, "w")
for s in string_elements:
f.write(s)
f.close()
\ No newline at end of file
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