Fixed references to common library

libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd

@@ -26,13 +26,13 @@
 -- > as 10
 -- > run -all  -- signal tb_end will stop the simulation by stopping the clk
 
-LIBRARY IEEE, technology_lib, tech_mult_lib, ip_stratixiv_mult_lib;
+LIBRARY IEEE, common_lib, technology_lib, tech_mult_lib, ip_stratixiv_mult_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
 USE technology_lib.technology_select_pkg.ALL;
-USE work.common_pkg.ALL;
-USE work.common_lfsr_sequences_pkg.ALL;
-USE work.tb_common_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_lfsr_sequences_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
 
 
 ENTITY tb_common_complex_mult IS
@@ -172,7 +172,7 @@ BEGIN
   out_result_re <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "RE", g_out_dat_w);
   out_result_im <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "IM", g_out_dat_w);
   
-  u_result_re : ENTITY work.common_pipeline
+  u_result_re : ENTITY common_lib.common_pipeline
   GENERIC MAP (
     g_representation => "SIGNED",
     g_pipeline       => c_pipeline,
@@ -188,7 +188,7 @@ BEGIN
     out_dat => result_re_expected
   );
   
-  u_result_im : ENTITY work.common_pipeline
+  u_result_im : ENTITY common_lib.common_pipeline
   GENERIC MAP (
     g_representation => "SIGNED",
     g_pipeline       => c_pipeline,
@@ -204,7 +204,7 @@ BEGIN
     out_dat => result_im_expected
   );
   
-  u_result_val_expected : ENTITY work.common_pipeline_sl
+  u_result_val_expected : ENTITY common_lib.common_pipeline_sl
   GENERIC MAP (
     g_pipeline    => c_pipeline,
     g_reset_value => 0

libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd

@@ -26,11 +26,11 @@
 --   > as 10
 --   > run -all
 
-LIBRARY IEEE;
+LIBRARY IEEE, common_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
-USE work.common_pkg.ALL;
-USE work.tb_common_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
 
 
 ENTITY tb_common_mult IS
@@ -161,7 +161,7 @@ BEGIN
   END PROCESS;
   
   -- pipeline inputs to ease comparison in the Wave window
-  u_in_a_pipeline : ENTITY work.common_pipeline
+  u_in_a_pipeline : ENTITY common_lib.common_pipeline
   GENERIC MAP (
     g_representation => "SIGNED",
     g_pipeline       => c_pipeline,
@@ -177,7 +177,7 @@ BEGIN
     out_dat => in_a_p
   );
   
-  u_in_b_pipeline : ENTITY work.common_pipeline
+  u_in_b_pipeline : ENTITY common_lib.common_pipeline
   GENERIC MAP (
     g_representation => "SIGNED",
     g_pipeline       => c_pipeline,
@@ -211,7 +211,7 @@ BEGIN
   sresult_stratix4 <= sresult_arr_stratix4(g_out_dat_w-1 DOWNTO 0);
   uresult_stratix4 <= uresult_arr_stratix4(g_out_dat_w-1 DOWNTO 0);
   
-  u_sresult : ENTITY work.common_pipeline
+  u_sresult : ENTITY common_lib.common_pipeline
   GENERIC MAP (
     g_representation => "SIGNED",
     g_pipeline       => c_pipeline,
@@ -227,7 +227,7 @@ BEGIN
     out_dat => sresult_expected
   );
   
-  u_uresult : ENTITY work.common_pipeline
+  u_uresult : ENTITY common_lib.common_pipeline
   GENERIC MAP (
     g_representation => "UNSIGNED",
     g_pipeline       => c_pipeline,

libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd

@@ -19,10 +19,10 @@
 --
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE;
+LIBRARY IEEE, common_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
-USE work.common_pkg.ALL;
+USE common_lib.common_pkg.ALL;
 
 
 ENTITY tb_common_mult_add2 IS
@@ -168,7 +168,7 @@ BEGIN
   
   out_result <= func_result(in_a0, in_b0, in_a1, in_b1);
   
-  u_result : ENTITY work.common_pipeline
+  u_result : ENTITY common_lib.common_pipeline
   GENERIC MAP (
     g_representation => "SIGNED",
     g_pipeline       => c_pipeline,