Add missing re and im values to v_last. Used in...

Add missing re and im values to v_last. Used in tb_dp_deinterleave_one_to_n_to_one.vhd and tb_dp_deinterleave_interleave_to_one.vhd

libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd

@@ -179,10 +179,15 @@ begin
     -- . account for g_pkt_len
     v_last.data    := INCR_UVEC(v_sosi.data, g_pkt_len - 1);
     v_last.data    := RESIZE_DP_DATA(v_last.data(g_in_dat_w - 1 downto 0));  -- wrap when >= 2**g_in_dat_w
+    v_last.re      := INCR_UVEC(v_sosi.re, g_pkt_len - 1);
+    v_last.re      := RESIZE_DP_DSP_DATA(v_last.re(g_in_dat_w - 1 downto 0));  -- wrap when >= 2**g_in_dat_w
+    v_last.im      := INCR_UVEC(v_sosi.im, g_pkt_len - 1);
+    v_last.im      := RESIZE_DP_DSP_DATA(v_last.im(g_in_dat_w - 1 downto 0));  -- wrap when >= 2**g_in_dat_w
     last_snk_in <= v_last;
 
     -- Signal end of stimuli
-    proc_common_wait_some_cycles(clk, g_wait_last_evt);  -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+    -- . latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+    proc_common_wait_some_cycles(clk, g_wait_last_evt);
     proc_common_gen_pulse(clk, last_snk_in_evt);
     proc_common_wait_some_cycles(clk, 50);
     tb_end <= '1';