Use '_arr' in sim_xaui.vhd.

libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd

@@ -198,19 +198,19 @@ BEGIN
   
       cal_rec_clk             => cal_rec_clk,
     
-      tx_clk               => tx_clk,
-      rx_clk               => i_rx_clk,
+      tx_clk_arr              => tx_clk,
+      rx_clk_arr              => i_rx_clk,
      
-      crc_rx_ready         => crc_rx_ready,
-      crc_tx_ready         => crc_tx_ready,
+      crc_rx_ready_arr        => crc_rx_ready,
+      crc_tx_ready_arr        => crc_tx_ready,
   
-      a_rx_channelaligned  => a_rx_channelaligned,
+      a_rx_channelaligned_arr => a_rx_channelaligned,
   
-      xgmii_tx_dc          => xgmii_tx_dc,
-      xgmii_rx_dc          => xgmii_rx_dc,
+      xgmii_tx_dc_arr         => xgmii_tx_dc,
+      xgmii_rx_dc_arr         => xgmii_rx_dc,
   
-      xaui_rx              => xaui_rx,
-      xaui_tx              => xaui_tx
+      xaui_rx_arr             => xaui_rx,
+      xaui_tx_arr             => xaui_tx
     );
   END GENERATE;  
 

libraries/io/tr_xaui/tb/vhdl/sim_xaui.vhd

@@ -37,19 +37,19 @@ ENTITY sim_xaui IS
     -- Calibration & reconfig clock
     cal_rec_clk             : IN  STD_LOGIC;
  
-    tx_clk                  : IN  STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
-    rx_clk                  : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
+    tx_clk_arr              : IN  STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
+    rx_clk_arr              : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
    
-    crc_rx_ready            : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); --crc = synchronous to Cal_Rec_Clk
-    crc_tx_ready            : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
+    crc_rx_ready_arr        : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); --crc = synchronous to Cal_Rec_Clk
+    crc_tx_ready_arr        : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
 
-    a_rx_channelaligned     : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
+    a_rx_channelaligned_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
 
-    xgmii_tx_dc             : IN  t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
-    xgmii_rx_dc             : OUT t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
+    xgmii_tx_dc_arr         : IN  t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
+    xgmii_rx_dc_arr         : OUT t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
 
-    xaui_rx                 : IN  t_xaui_arr(g_nof_xaui-1 DOWNTO 0);
-    xaui_tx                 : OUT t_xaui_arr(g_nof_xaui-1 DOWNTO 0)
+    xaui_rx_arr             : IN  t_xaui_arr(g_nof_xaui-1 DOWNTO 0);
+    xaui_tx_arr             : OUT t_xaui_arr(g_nof_xaui-1 DOWNTO 0)
   );
 END sim_xaui;
 
@@ -61,23 +61,23 @@ ARCHITECTURE wrap OF sim_xaui IS
   CONSTANT c_xaui_serdes_line_rate : NATURAL := 3125;
 
   --XGMII control bits (one for each XGMII lane):
-  SIGNAL xgmii_tx_c                : t_xgmii_c_arr(g_nof_xaui-1 DOWNTO 0);
-  SIGNAL xgmii_rx_c                : t_xgmii_c_arr(g_nof_xaui-1 DOWNTO 0);
+  SIGNAL xgmii_tx_c_arr            : t_xgmii_c_arr(g_nof_xaui-1 DOWNTO 0);
+  SIGNAL xgmii_rx_c_arr            : t_xgmii_c_arr(g_nof_xaui-1 DOWNTO 0);
   
   --XGMII data
-  SIGNAL xgmii_tx_d                : t_xgmii_d_arr(g_nof_xaui-1 DOWNTO 0);
-  SIGNAL xgmii_rx_d                : t_xgmii_d_arr(g_nof_xaui-1 DOWNTO 0);
+  SIGNAL xgmii_tx_d_arr            : t_xgmii_d_arr(g_nof_xaui-1 DOWNTO 0);
+  SIGNAL xgmii_rx_d_arr            : t_xgmii_d_arr(g_nof_xaui-1 DOWNTO 0);
  
 BEGIN
 
-  rx_clk <= tx_clk;
+  rx_clk_arr <= tx_clk_arr;
  
   gen_nof_xaui : FOR i IN g_nof_xaui-1 DOWNTO 0 GENERATE
 
-    xgmii_tx_d(i) <= xgmii_d(xgmii_tx_dc(i));
-    xgmii_tx_c(i) <= xgmii_c(xgmii_tx_dc(i));
+    xgmii_tx_d_arr(i) <= xgmii_d(xgmii_tx_dc_arr(i));
+    xgmii_tx_c_arr(i) <= xgmii_c(xgmii_tx_dc_arr(i));
 
-    xgmii_rx_dc(i) <= xgmii_dc(xgmii_rx_d(i), xgmii_rx_c(i));
+    xgmii_rx_dc_arr(i) <= xgmii_dc(xgmii_rx_d_arr(i), xgmii_rx_c_arr(i));
     
     u_areset_tx_rdy : ENTITY common_lib.common_areset
     GENERIC MAP(
@@ -87,7 +87,7 @@ BEGIN
     PORT MAP(
       clk     => cal_rec_clk,
       in_rst  => '0',
-      out_rst => crc_tx_ready(i)
+      out_rst => crc_tx_ready_arr(i)
     );    
 
     u_areset_rx_rdy : ENTITY common_lib.common_areset
@@ -98,7 +98,7 @@ BEGIN
     PORT MAP(
       clk     => cal_rec_clk,
       in_rst  => '0',
-      out_rst => crc_rx_ready(i)
+      out_rst => crc_rx_ready_arr(i)
     );   
 
     u_areset_rx_channelaligned : ENTITY common_lib.common_areset
@@ -109,7 +109,7 @@ BEGIN
     PORT MAP(
       clk     => cal_rec_clk,
       in_rst  => '0',
-      out_rst => a_rx_channelaligned(i)
+      out_rst => a_rx_channelaligned_arr(i)
     );    
 
     gen_serdes: FOR j IN c_nof_xaui_lanes-1 DOWNTO 0 GENERATE
@@ -124,10 +124,10 @@ BEGIN
         tr_clk             => tr_clk,  
         tr_rst             => tr_rst,
          
-        tx_in_data         => xgmii_tx_d(i)(j*c_xaui_serdes_data_w+c_xaui_serdes_data_w-1 DOWNTO j*c_xaui_serdes_data_w),
-        tx_in_ctrl         => xgmii_tx_c(i)(j*c_xaui_serdes_ctrl_w+c_xaui_serdes_ctrl_w-1 DOWNTO j*c_xaui_serdes_ctrl_w),
+        tx_in_data         => xgmii_tx_d_arr(i)(j*c_xaui_serdes_data_w+c_xaui_serdes_data_w-1 DOWNTO j*c_xaui_serdes_data_w),
+        tx_in_ctrl         => xgmii_tx_c_arr(i)(j*c_xaui_serdes_ctrl_w+c_xaui_serdes_ctrl_w-1 DOWNTO j*c_xaui_serdes_ctrl_w),
     
-        tx_out             => xaui_tx(i)(j)
+        tx_out             => xaui_tx_arr(i)(j)
       );
 
       u_des: ENTITY tr_nonbonded_lib.deserializer 
@@ -140,10 +140,10 @@ BEGIN
         tr_clk             => tr_clk,  
         tr_rst             => tr_rst,
          
-        rx_out_data        => xgmii_rx_d(i)(j*c_xaui_serdes_data_w+c_xaui_serdes_data_w-1 DOWNTO j*c_xaui_serdes_data_w),
-        rx_out_ctrl        => xgmii_rx_c(i)(j*c_xaui_serdes_ctrl_w+c_xaui_serdes_ctrl_w-1 DOWNTO j*c_xaui_serdes_ctrl_w),
+        rx_out_data        => xgmii_rx_d_arr(i)(j*c_xaui_serdes_data_w+c_xaui_serdes_data_w-1 DOWNTO j*c_xaui_serdes_data_w),
+        rx_out_ctrl        => xgmii_rx_c_arr(i)(j*c_xaui_serdes_ctrl_w+c_xaui_serdes_ctrl_w-1 DOWNTO j*c_xaui_serdes_ctrl_w),
     
-        rx_in              => xaui_rx(i)(j)
+        rx_in              => xaui_rx_arr(i)(j)
       );
 
     END GENERATE;