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Commit 91c65aea authored by Eric Kooistra's avatar Eric Kooistra
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Use new tech_eth_10g_clocks.vhd to connect the clocks at eth_10g top level.

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libraries/technology/eth_10g/hdllib.cfg
+ 1
− 0
View file @ 91c65aea
......@@ -9,6 +9,7 @@ build_dir_synth = $HDL_BUILD_DIR
synth_files =
tech_eth_10g_stratixiv.vhd
tech_eth_10g_arria10.vhd
tech_eth_10g_clocks.vhd
tech_eth_10g.vhd
test_bench_files =
......
libraries/technology/eth_10g/tb_tech_eth_10g.vhd
+ 55
− 44
View file @ 91c65aea
......@@ -102,26 +102,22 @@ ARCHITECTURE tb OF tb_tech_eth_10g IS
SIGNAL mm_clk : STD_LOGIC := '0'; -- memory-mapped bus clock
SIGNAL mm_rst : STD_LOGIC; -- reset synchronous with mm_clk
-- . 10base_r clocks
SIGNAL tr_ref_clk_644 : STD_LOGIC := '1';
SIGNAL clk_312 : STD_LOGIC;
SIGNAL clk_156 : STD_LOGIC;
SIGNAL rst_156 : STD_LOGIC;
-- . XAUI clocks
SIGNAL tr_ref_clk_156 : STD_LOGIC := '1';
SIGNAL tr_ref_rst_156 : STD_LOGIC := '1';
SIGNAL tx_rst_arr : STD_LOGIC_VECTOR(0 DOWNTO 0);
-- External reference clocks
SIGNAL tr_ref_clk_644 : STD_LOGIC := '1'; -- 10GBASE-R
SIGNAL tr_ref_clk_312 : STD_LOGIC; -- 10GBASE-R
SIGNAL tr_ref_clk_156 : STD_LOGIC := '1'; -- 10GBASE-R or XAUI
SIGNAL tr_ref_rst_156 : STD_LOGIC; -- 10GBASE-R or XAUI
-- XAUI clocks
SIGNAL tx_rst_arr_out : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL rx_clk_arr_out : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL rx_rst_arr : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL rx_rst_arr_out : STD_LOGIC_VECTOR(0 DOWNTO 0);
-- . Test bench top level clocks
SIGNAL tb_ref_clk_644 : STD_LOGIC;
SIGNAL tb_ref_clk_312 : STD_LOGIC;
SIGNAL tb_ref_clk_156 : STD_LOGIC;
SIGNAL tb_ref_rst_156 : STD_LOGIC;
SIGNAL tb_clk_312 : STD_LOGIC;
SIGNAL tb_clk_156 : STD_LOGIC;
SIGNAL tb_rst_156 : STD_LOGIC;
SIGNAL tb_tx_clk : STD_LOGIC;
SIGNAL tb_tx_rst : STD_LOGIC;
SIGNAL tb_rx_clk : STD_LOGIC;
......@@ -220,21 +216,15 @@ BEGIN
rx_siso_arr(0) <= rx_siso;
rx_sosi <= rx_sosi_arr(0);
-- Connect the clocks from test bench top level (down such that they have their rising_edge() aligned without any delta-delay)
gen_tb_clocks_xaui : IF g_technology=c_tech_stratixiv GENERATE
-- Generate reference clocks
gen_ref_clocks_xaui : IF g_technology=c_tech_stratixiv GENERATE
tr_ref_clk_644 <= 'X';
tr_ref_clk_312 <= 'X';
tr_ref_clk_156 <= NOT tr_ref_clk_156 AFTER g_ref_clk_156_period/2;
tr_ref_rst_156 <= '0' AFTER g_ref_clk_156_period*5;
tb_ref_clk_156 <= tr_ref_clk_156;
tb_ref_rst_156 <= tr_ref_rst_156;
tb_tx_clk <= tr_ref_clk_156;
tb_rx_clk <= rx_clk_arr_out(0);
tb_tx_rst <= tx_rst_arr(0);
tb_rx_rst <= rx_rst_arr(0);
END GENERATE;
gen_tb_clocks_10gbase_r : IF g_technology=c_tech_arria10 GENERATE
gen_ref_clocks_10gbase_r : IF g_technology=c_tech_arria10 GENERATE
tr_ref_clk_644 <= NOT tr_ref_clk_644 AFTER g_ref_clk_644_period/2;
pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
......@@ -243,20 +233,47 @@ BEGIN
)
PORT MAP (
refclk_644 => tr_ref_clk_644,
clk_156 => clk_156,
clk_312 => clk_312,
rst_156 => rst_156,
clk_156 => tr_ref_clk_156,
clk_312 => tr_ref_clk_312,
rst_156 => tr_ref_rst_156,
rst_312 => OPEN
);
tb_ref_clk_644 <= tr_ref_clk_644;
tb_clk_312 <= clk_312;
tb_clk_156 <= clk_156;
tb_rst_156 <= rst_156;
tb_tx_clk <= clk_156;
tb_rx_clk <= clk_156;
END GENERATE;
-- Apply the clocks from top level down such that they have their rising_edge() aligned without any delta-delay
u_tech_eth_10g_clocks : ENTITY work.tech_eth_10g_clocks
GENERIC MAP (
g_technology => g_technology,
g_nof_channels => 1
)
PORT MAP (
-- Input clocks
-- . Reference
tr_ref_clk_644 => tr_ref_clk_644,
tr_ref_clk_312 => tr_ref_clk_312,
tr_ref_clk_156 => tr_ref_clk_156,
tr_ref_rst_156 => tr_ref_rst_156,
-- . XAUI
tx_rst_arr => tx_rst_arr_out,
rx_clk_arr => rx_clk_arr_out,
rx_rst_arr => rx_rst_arr_out,
-- Output clocks
-- . Reference
eth_ref_clk_644 => tb_ref_clk_644,
eth_ref_clk_312 => tb_ref_clk_312,
eth_ref_clk_156 => tb_ref_clk_156,
eth_ref_rst_156 => tb_ref_rst_156,
-- . Data
eth_tx_clk_arr(0) => tb_tx_clk,
eth_tx_rst_arr(0) => tb_tx_rst,
eth_rx_clk_arr(0) => tb_rx_clk,
eth_rx_rst_arr(0) => tb_rx_rst
);
no_dut : IF c_st_loopback=TRUE GENERATE
rx_sosi <= tx_sosi;
tx_siso <= rx_siso;
......@@ -270,12 +287,12 @@ BEGIN
g_sim_level => g_sim_level,
g_nof_channels => 1,
g_link_status_check => g_link_status_check,
--g_pre_header_padding => FALSE
g_pre_header_padding => TRUE
)
PORT MAP (
-- Transceiver PLL reference clock
tr_ref_clk_644 => tb_ref_clk_644,
tr_ref_clk_312 => tb_ref_clk_312,
tr_ref_clk_156 => tb_ref_clk_156,
tr_ref_rst_156 => tb_ref_rst_156,
......@@ -286,18 +303,12 @@ BEGIN
mac_mosi => mm_mosi, -- CSR = control status register
mac_miso => mm_miso,
-- Clocks
-- . 10GBASE-R
clk_312 => tb_clk_312,
clk_156 => tb_clk_156, -- 156.25 MHz local reference
rst_156 => tb_rst_156,
-- . XAUI
tx_clk_arr(0) => tb_tx_clk, -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
tx_rst_arr => tx_rst_arr,
-- XAUI clocks
tx_clk_arr_in(0) => tb_tx_clk, -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
tx_rst_arr_out => tx_rst_arr_out,
rx_clk_arr_out => rx_clk_arr_out,
rx_clk_arr_in(0) => tb_rx_clk, -- externally connect to rx_clk_arr_out to avoid clock delta-delay
rx_rst_arr => rx_rst_arr,
rx_rst_arr_out => rx_rst_arr_out,
-- ST
tx_snk_in_arr => tx_sosi_arr, -- 64 bit data @ 156 tb_tx_clk
......
libraries/technology/eth_10g/tech_eth_10g.vhd
+ 29
− 27
View file @ 91c65aea
......@@ -23,11 +23,15 @@
-- Purpose: Combine mac_10g and 10gbase_r
-- Description:
-- . For c_tech_stratixiv: not available (yet)
-- . For c_tech_stratixiv:
--
-- tr_ref_clk_156
-- tr_ref_rst_156
-- cal_rec_clk
-- cal_rec_clk -->
-- tr_ref_clk_156 -->
-- tr_ref_rst_156 -->
--
-- tx_clk_arr_in -->
-- rx_clk_arr_out <--
-- rx_clk_arr_in -->
-- ___________________
-- | |
-- tx_snk --->|tech_ |---> xaui_tx_arr
......@@ -39,7 +43,10 @@
--
-- . For c_tech_arria10:
--
-- tr_ref_clk_644
-- tr_ref_clk_644 -->
-- tr_ref_clk_312 -->
-- tr_ref_clk_156 -->
-- tr_ref_rst_156 -->
-- ___________________
-- | |
-- tx_snk --->|tech_ |---> serial_tx
......@@ -72,24 +79,19 @@ ENTITY tech_eth_10g IS
PORT (
-- Transceiver PLL reference clock
tr_ref_clk_644 : IN STD_LOGIC := '0'; -- 644.531250 MHz for 10GBASE-R
tr_ref_clk_156 : IN STD_LOGIC := '0'; -- 156.25 MHz for XAUI
tr_ref_rst_156 : IN STD_LOGIC := '0'; -- for XAUI
tr_ref_clk_312 : IN STD_LOGIC := '0'; -- 312.5 MHz for 10GBASE-R
tr_ref_clk_156 : IN STD_LOGIC := '0'; -- 156.25 MHz for 10GBASE-R or for XAUI
tr_ref_rst_156 : IN STD_LOGIC := '0'; -- for 10GBASE-R or for XAUI
-- Calibration & reconfig clock
cal_rec_clk : IN STD_LOGIC := '0'; -- for XAUI;
-- Data clocks and reset
-- . 10GBASE-R
clk_312 : IN STD_LOGIC := '0';
clk_156 : IN STD_LOGIC := '0';
rst_156 : IN STD_LOGIC := '0';
-- . XAUI
tx_clk_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0'); -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
tx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
-- XAUI clocks
tx_clk_arr_in : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0'); -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr_in or connect rx_clk_arr to tx_clk_arr_in
tx_rst_arr_out : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
rx_clk_arr_out : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
rx_clk_arr_in : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0'); -- externally connect to rx_clk_arr_out to avoid clock delta-delay
rx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
rx_rst_arr_out : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
-- MM
mm_clk : IN STD_LOGIC;
......@@ -141,11 +143,11 @@ BEGIN
cal_rec_clk => cal_rec_clk,
-- Data clocks
tx_clk_arr => tx_clk_arr,
tx_rst_arr => tx_rst_arr,
tx_clk_arr_in => tx_clk_arr_in,
tx_rst_arr_out => tx_rst_arr_out,
rx_clk_arr_out => rx_clk_arr_out,
rx_clk_arr_in => rx_clk_arr_in,
rx_rst_arr => rx_rst_arr,
rx_rst_arr_out => rx_rst_arr_out,
-- MM
mm_clk => mm_clk,
......@@ -158,10 +160,10 @@ BEGIN
xaui_miso => xaui_miso,
-- ST
tx_snk_in_arr => tx_snk_in_arr, -- 64 bit data @ clk_156
tx_snk_in_arr => tx_snk_in_arr, -- 64 bit data @ tx_clk_arr_in (156.25 MHz)
tx_snk_out_arr => tx_snk_out_arr,
rx_src_out_arr => rx_src_out_arr, -- 64 bit data @ clk_156
rx_src_out_arr => rx_src_out_arr, -- 64 bit data @ rx_clk_arr (156.25 MHz)
rx_src_in_arr => rx_src_in_arr,
-- Serial IO
......@@ -184,9 +186,9 @@ BEGIN
tr_ref_clk_644 => tr_ref_clk_644,
-- Data clocks
clk_312 => clk_312,
clk_156 => clk_156,
rst_156 => rst_156,
clk_312 => tr_ref_clk_312,
clk_156 => tr_ref_clk_156,
rst_156 => tr_ref_rst_156,
-- MM
mm_clk => mm_clk,
......@@ -196,10 +198,10 @@ BEGIN
mac_miso => mac_miso,
-- ST
tx_snk_in_arr => tx_snk_in_arr, -- 64 bit data @ clk_156
tx_snk_in_arr => tx_snk_in_arr, -- 64 bit data @ tr_ref_clk_156
tx_snk_out_arr => tx_snk_out_arr,
rx_src_out_arr => rx_src_out_arr, -- 64 bit data @ clk_156
rx_src_out_arr => rx_src_out_arr, -- 64 bit data @ tr_ref_clk_156
rx_src_in_arr => rx_src_in_arr,
-- Serial
......
libraries/technology/eth_10g/tech_eth_10g_clocks.vhd 0 → 100644
+ 96
− 0
View file @ 91c65aea
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Connect the clocks for the tech_eth_10g.
-- Description:
-- Apply the clocks from top level down, such that they have their
-- rising_edge() aligned without any delta-delay. The reference clocks
-- are also reassigned to preserve same delta-cycle phase as for the data
-- clocks.
LIBRARY IEEE, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
ENTITY tech_eth_10g_clocks IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_nof_channels : NATURAL := 1
);
PORT (
-- Input clocks
-- . Reference
tr_ref_clk_644 : IN STD_LOGIC := 'X'; -- 10GBASE-R
tr_ref_clk_312 : IN STD_LOGIC := 'X'; -- 10GBASE-R
tr_ref_clk_156 : IN STD_LOGIC := 'X'; -- 10GBASE-R or XAUI
tr_ref_rst_156 : IN STD_LOGIC := 'X'; -- 10GBASE-R or XAUI
-- . XAUI
tx_rst_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0');
rx_clk_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'X');
rx_rst_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0');
-- Output clocks
-- . Reference
eth_ref_clk_644 : OUT STD_LOGIC;
eth_ref_clk_312 : OUT STD_LOGIC;
eth_ref_clk_156 : OUT STD_LOGIC;
eth_ref_rst_156 : OUT STD_LOGIC;
-- . Data
eth_tx_clk_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
eth_tx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
eth_rx_clk_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
eth_rx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
);
END tech_eth_10g_clocks;
ARCHITECTURE str OF tech_eth_10g_clocks IS
BEGIN
-- Reference
eth_ref_clk_644 <= tr_ref_clk_644;
eth_ref_clk_312 <= tr_ref_clk_312;
eth_ref_clk_156 <= tr_ref_clk_156;
eth_ref_rst_156 <= tr_ref_rst_156;
gen_clocks_xaui : IF g_technology=c_tech_stratixiv GENERATE
-- Data
eth_tx_clk_arr <= (OTHERS=>tr_ref_clk_156);
eth_tx_rst_arr <= tx_rst_arr;
eth_rx_clk_arr <= rx_clk_arr;
eth_rx_rst_arr <= rx_rst_arr;
END GENERATE;
gen_clocks_10gbase_r : IF g_technology=c_tech_arria10 GENERATE
eth_tx_clk_arr <= (OTHERS=>tr_ref_clk_156);
eth_tx_rst_arr <= (OTHERS=>tr_ref_rst_156);
eth_rx_clk_arr <= (OTHERS=>tr_ref_clk_156);
eth_rx_rst_arr <= (OTHERS=>tr_ref_rst_156);
END GENERATE;
END str;
libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd
+ 20
− 20
View file @ 91c65aea
......@@ -71,11 +71,11 @@ ENTITY tech_eth_10g_stratixiv IS
cal_rec_clk : IN STD_LOGIC;
-- Data clocks
tx_clk_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
tx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
tx_clk_arr_in : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr_in or connect rx_clk_arr to tx_clk_arr_in
tx_rst_arr_out : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
rx_clk_arr_out : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
rx_clk_arr_in : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- externally connect to rx_clk_arr_out to avoid clock delta-delay
rx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
rx_rst_arr_out : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
-- MM
mm_clk : IN STD_LOGIC;
......@@ -88,7 +88,7 @@ ENTITY tech_eth_10g_stratixiv IS
xaui_miso : OUT t_mem_miso;
-- ST
tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ 156 MHz tx_clk_arr
tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ 156 MHz tx_clk_arr_in
tx_snk_out_arr : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ 156 MHz rx_clk_arr_in
......@@ -108,13 +108,13 @@ ARCHITECTURE str OF tech_eth_10g_stratixiv IS
SIGNAL mac_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
-- ST
SIGNAL i_tx_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL i_rx_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL i_tx_rst_arr_out : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL i_rx_rst_arr_out : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL txc_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- tx_ready in tx_clk_arr domain, can be used for xon flow control
SIGNAL txc_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- tx_ready in tx_clk_arr_in domain, can be used for xon flow control
SIGNAL rxc_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- rx_ready in rx_clk_arr domain, typically leave not connected
SIGNAL txc_rx_channelaligned_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- rx_channelaligned in tx_clk_arr domain, from PHY XAUI, indicates
SIGNAL txc_rx_channelaligned_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- rx_channelaligned in tx_clk_arr_in domain, from PHY XAUI, indicates
-- that all 4 RX channels are aligned when asserted
-- XON control
......@@ -129,11 +129,11 @@ ARCHITECTURE str OF tech_eth_10g_stratixiv IS
BEGIN
-- Clocks and reset
tx_rst_arr <= i_tx_rst_arr;
rx_rst_arr <= i_rx_rst_arr;
tx_rst_arr_out <= i_tx_rst_arr_out;
rx_rst_arr_out <= i_rx_rst_arr_out;
i_tx_rst_arr <= NOT txc_tx_ready_arr;
i_rx_rst_arr <= NOT rxc_rx_ready_arr;
i_tx_rst_arr_out <= NOT txc_tx_ready_arr;
i_rx_rst_arr_out <= NOT rxc_rx_ready_arr;
xgmii_tx_ready_arr <= txc_tx_ready_arr;
......@@ -141,10 +141,10 @@ BEGIN
tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready; -- pass on MAC cycle accurate backpressure
p_xon_flow_control : PROCESS(tx_clk_arr)
p_xon_flow_control : PROCESS(tx_clk_arr_in)
VARIABLE v_xgmii_link_status : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0);
BEGIN
IF rising_edge(tx_clk_arr(I)) THEN
IF rising_edge(tx_clk_arr_in(I)) THEN
tx_snk_out_arr(I).xon <= '0';
v_xgmii_link_status := xgmii_link_status_arr(I) AND g_link_status_check; -- use mask to check Tx, Rx, both or none.
IF xgmii_tx_ready_arr(I)='1' AND txc_rx_channelaligned_arr(I)='1' AND v_xgmii_link_status="00" THEN
......@@ -166,13 +166,13 @@ BEGIN
csr_miso => mac_miso_arr(I),
-- ST
tx_clk_156 => tx_clk_arr(I),
tx_rst => i_tx_rst_arr(I),
tx_clk_156 => tx_clk_arr_in(I),
tx_rst => i_tx_rst_arr_out(I),
tx_snk_in => tx_snk_in_arr(I), -- 64 bit data
tx_snk_out => mac_snk_out_arr(I),
rx_clk_156 => rx_clk_arr_in(I),
rx_rst => i_rx_rst_arr(I),
rx_rst => i_rx_rst_arr_out(I),
rx_src_out => rx_src_out_arr(I), -- 64 bit data
rx_src_in => rx_src_in_arr(I),
......@@ -206,14 +206,14 @@ BEGIN
xaui_miso => xaui_miso,
-- XGMII interface
tx_clk_arr => tx_clk_arr,
tx_clk_arr => tx_clk_arr_in,
rx_clk_arr_out => rx_clk_arr_out,
rx_clk_arr_in => rx_clk_arr_in,
txc_tx_ready_arr => txc_tx_ready_arr, -- tx_ready in tx_clk_arr domain, can be used for xon flow control
txc_tx_ready_arr => txc_tx_ready_arr, -- tx_ready in tx_clk_arr_in domain, can be used for xon flow control
rxc_rx_ready_arr => rxc_rx_ready_arr, -- rx_ready in rx_clk_arr domain, typically leave not connected
txc_rx_channelaligned_arr => txc_rx_channelaligned_arr, -- rx_channelaligned in tx_clk_arr domain, indicates that all 4 RX channels are aligned when asserted
txc_rx_channelaligned_arr => txc_rx_channelaligned_arr, -- rx_channelaligned in tx_clk_arr_in domain, indicates that all 4 RX channels are aligned when asserted
xgmii_tx_dc_arr => xgmii_tx_dc_arr,
xgmii_rx_dc_arr => xgmii_rx_dc_arr,
......
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