Added ASSERTs to check MM access flow control.

libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd

@@ -42,6 +42,8 @@
 --     . '1' for g_prsg_w mm_clk cycles
 --     . '0' for g_prsg_w-1 mm_clk cycles
 -- Remarks:
+-- . To some extend the ASSERTs check the flow control. The testbench has to
+--   verify the rddata to ensure more test coverage.
 --
 -------------------------------------------------------------------------------
 
@@ -72,10 +74,12 @@ ARCHITECTURE rtl OF mm_waitrequest_model IS
   CONSTANT c_prsg_init     : NATURAL := g_seed + 1;  -- PRSG init must be > 0
   
   SIGNAL prsg              : STD_LOGIC_VECTOR(g_prsg_w-1 DOWNTO 0) := TO_UVEC(c_prsg_init, g_prsg_w);
-  SIGNAL nxt_prsg          : STD_LOGIC_VECTOR(g_prsg_w-1 DOWNTO 0);
   
   SIGNAL waitrequest       : STD_LOGIC;
 
+  SIGNAL prev_bus_mosi     : t_mem_mosi;
+  SIGNAL prev_waitrequest  : STD_LOGIC;
+  
 BEGIN
 
   no_waitrequest : IF g_waitrequest=FALSE GENERATE
@@ -93,7 +97,11 @@ BEGIN
     p_reg : PROCESS(mm_clk)
     BEGIN       
       IF rising_edge(mm_clk) THEN
-        prsg <= func_common_random(prsg);
+        -- random waitrequest flow control
+        prsg             <= func_common_random(prsg);
+        -- check MM access
+        prev_bus_mosi    <= bus_mosi;
+        prev_waitrequest <= waitrequest;
       END IF;
     END PROCESS;
     
@@ -114,6 +122,17 @@ BEGIN
       slave_mosi.rd <= bus_mosi.rd AND NOT waitrequest;
     END PROCESS;
     
+    -- Verify that MM access is not removed before it is acknowledged by waitrequest
+    p_verify : PROCESS(bus_mosi, prev_bus_mosi, prev_waitrequest)
+    BEGIN
+      IF prev_waitrequest = '1' THEN
+        IF prev_bus_mosi.wr = '1' AND bus_mosi.wr = '0' THEN REPORT "Aborted slave write." SEVERITY ERROR; END IF;
+        IF prev_bus_mosi.rd = '1' AND bus_mosi.rd = '0' THEN REPORT "Aborted slave read." SEVERITY ERROR; END IF;
+        IF prev_bus_mosi.wr = '1' AND bus_mosi.address /= prev_bus_mosi.address THEN REPORT "Address change during pending slave write." SEVERITY ERROR; END IF;
+        IF prev_bus_mosi.rd = '1' AND bus_mosi.address /= prev_bus_mosi.address THEN REPORT "Address change during pending slave read." SEVERITY ERROR; END IF;
+      END IF;
+    END PROCESS;
+    
   END GENERATE;
   
 END rtl;