Add more assert logging.

libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd

@@ -263,9 +263,11 @@ BEGIN
       mon_latency_input_arr(I) <= TO_SINT(reg_input_monitor_cipo.rddata(31 DOWNTO 0));
       proc_common_wait_some_cycles(mm_clk, 1);
       IF g_lost_input = TRUE AND I = c_nof_streams-1 THEN
-        ASSERT mon_latency_input_arr(I) = -1 REPORT "Wrong input BSN monitor latency timeout for input " & int_to_str(I) SEVERITY ERROR;
+        ASSERT mon_latency_input_arr(I) = -1 REPORT "Wrong input BSN monitor latency timeout for input " & int_to_str(I) &
+          " (" & int_to_str(mon_latency_input_arr(I)) & " /= -1)" SEVERITY ERROR;
       ELSE
-        ASSERT mon_latency_input_arr(I) = func_input_delay(I) REPORT "Wrong input BSN monitor latency for input " & int_to_str(I) SEVERITY ERROR;
+        ASSERT mon_latency_input_arr(I) = func_input_delay(I) REPORT "Wrong input BSN monitor latency for input " & int_to_str(I) &
+          " (" & int_to_str(mon_latency_input_arr(I)) & " /= " & int_to_str(func_input_delay(I)) & ")" SEVERITY ERROR;
       END IF;
     END LOOP;