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Commit 90e42fcb authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Added Second ss_parallel stage (+ FIFOs and 16b->8b->16b rewiring) to top 

 level;
-Added Python script to generate SS selection HEX files. Functionally this
 does no reordering, out=in (for 16b mode).
-Verified in sim.
parent 220bca7e
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