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Commit 909bf4f3 authored by Pieter Donker's avatar Pieter Donker
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another unb2 to unb2b change

parent 1b133e28
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...@@ -28,7 +28,7 @@ USE dp_lib.dp_stream_pkg.ALL; ...@@ -28,7 +28,7 @@ USE dp_lib.dp_stream_pkg.ALL;
USE technology_lib.technology_pkg.ALL; USE technology_lib.technology_pkg.ALL;
ENTITY unb2_board_10gbe IS ENTITY unb2b_board_10gbe IS
GENERIC ( GENERIC (
g_sim : BOOLEAN := FALSE; g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model
...@@ -70,17 +70,17 @@ ENTITY unb2_board_10gbe IS ...@@ -70,17 +70,17 @@ ENTITY unb2_board_10gbe IS
serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_macs-1 downto 0); serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_macs-1 downto 0);
serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_macs-1 downto 0) := (OTHERS=>'0') serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_macs-1 downto 0) := (OTHERS=>'0')
); );
END unb2_board_10gbe; END unb2b_board_10gbe;
ARCHITECTURE str OF unb2_board_10gbe IS ARCHITECTURE str OF unb2b_board_10gbe IS
SIGNAL tr_ref_clk_312 : STD_LOGIC; SIGNAL tr_ref_clk_312 : STD_LOGIC;
SIGNAL tr_ref_clk_156 : STD_LOGIC; SIGNAL tr_ref_clk_156 : STD_LOGIC;
SIGNAL tr_ref_rst_156 : STD_LOGIC; SIGNAL tr_ref_rst_156 : STD_LOGIC;
BEGIN BEGIN
u_unb2_board_clk644_pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks u_unb2b_board_clk644_pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
GENERIC MAP ( GENERIC MAP (
g_technology => g_technology g_technology => g_technology
) )
......
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