Skip to content
Snippets Groups Projects
Commit 90900478 authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
Browse files

weird svn problem

parent c8b9b30f
No related branches found
No related tags found
No related merge requests found
:0800000000074306C7000022BF
:0800010086080000080045001C
:080002002322000040007F11E1
:08000300BA530A6300010A0A66
:080004000A0A0FA00FA0230E51
:080005000000000000000000F3
:080006000000000000000000F2
:080007000000000000000000F1
:00000001FF
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2_board_lib, mm_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL; --?
USE common_lib.common_field_pkg.ALL; --?
USE common_lib.common_network_total_header_pkg.ALL; --?
USE common_lib.common_network_layers_pkg.ALL; --?
USE unb2_board_lib.unb2_board_pkg.ALL;
USE unb2_board_lib.unb2_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
--USE eth_lib.eth_pkg.ALL; --?
--USE technology_lib.technology_pkg.ALL; --?
--USE tech_tse_lib.tech_tse_pkg.ALL; --?
--USE tech_tse_lib.tb_tech_tse_pkg.ALL; --?
USE work.qsys_unb2_test_pkg.ALL;
ENTITY mmm_unb2_test IS
GENERIC (
g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_nof_streams : NATURAL;
g_bg_block_size : NATURAL;
g_hdr_field_arr : t_common_field_arr
);
PORT (
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
pout_wdi : OUT STD_LOGIC;
-- Manual WDI override
reg_wdi_mosi : OUT t_mem_mosi;
reg_wdi_miso : IN t_mem_miso;
-- system_info
reg_unb_system_info_mosi : OUT t_mem_mosi;
reg_unb_system_info_miso : IN t_mem_miso;
rom_unb_system_info_mosi : OUT t_mem_mosi;
rom_unb_system_info_miso : IN t_mem_miso;
-- UniBoard I2C sensors
reg_unb_sens_mosi : OUT t_mem_mosi;
reg_unb_sens_miso : IN t_mem_miso;
-- PPSH
reg_ppsh_mosi : OUT t_mem_mosi;
reg_ppsh_miso : IN t_mem_miso;
-- eth1g
eth1g_tse_mosi : OUT t_mem_mosi;
eth1g_tse_miso : IN t_mem_miso;
eth1g_reg_mosi : OUT t_mem_mosi;
eth1g_reg_miso : IN t_mem_miso;
eth1g_reg_interrupt : IN STD_LOGIC;
eth1g_ram_mosi : OUT t_mem_mosi;
eth1g_ram_miso : IN t_mem_miso;
-- EPCS read
reg_dpmm_data_mosi : OUT t_mem_mosi;
reg_dpmm_data_miso : IN t_mem_miso;
reg_dpmm_ctrl_mosi : OUT t_mem_mosi;
reg_dpmm_ctrl_miso : IN t_mem_miso;
-- EPCS write
reg_mmdp_data_mosi : OUT t_mem_mosi;
reg_mmdp_data_miso : IN t_mem_miso;
reg_mmdp_ctrl_mosi : OUT t_mem_mosi;
reg_mmdp_ctrl_miso : IN t_mem_miso;
-- EPCS status/control
reg_epcs_mosi : OUT t_mem_mosi;
reg_epcs_miso : IN t_mem_miso;
-- Remote Update
reg_remu_mosi : OUT t_mem_mosi;
reg_remu_miso : IN t_mem_miso;
-- bg
ram_diag_bg_mosi : OUT t_mem_mosi;
ram_diag_bg_miso : IN t_mem_miso;
reg_diag_bg_mosi : OUT t_mem_mosi;
reg_diag_bg_miso : IN t_mem_miso;
-- dp offload
reg_dp_offload_tx_mosi : OUT t_mem_mosi;
reg_dp_offload_tx_miso : IN t_mem_miso;
reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
reg_dp_offload_tx_hdr_dat_miso : IN t_mem_miso;
reg_dp_offload_tx_hdr_ovr_mosi : OUT t_mem_mosi;
reg_dp_offload_tx_hdr_ovr_miso : IN t_mem_miso;
reg_dp_offload_rx_hdr_dat_mosi : OUT t_mem_mosi;
reg_dp_offload_rx_hdr_dat_miso : IN t_mem_miso;
-- bsn monitor
reg_bsn_monitor_mosi : OUT t_mem_mosi;
reg_bsn_monitor_miso : IN t_mem_miso;
-- db
ram_diag_data_buf_mosi : OUT t_mem_mosi;
ram_diag_data_buf_miso : IN t_mem_miso;
reg_diag_data_buf_mosi : OUT t_mem_mosi;
reg_diag_data_buf_miso : IN t_mem_miso;
-- 10GbE
reg_tr_10GbE_mosi : OUT t_mem_mosi;
reg_tr_10GbE_miso : IN t_mem_miso
);
END mmm_unb2_test;
ARCHITECTURE str OF mmm_unb2_test IS
CONSTANT c_sim_node_nr : NATURAL := g_sim_node_nr;
CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";
-- Block generator
CONSTANT c_ram_diag_bg_addr_w : NATURAL := ceil_log2(g_nof_streams* pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
CONSTANT c_reg_dp_offload_tx_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_tx_adr_w));
CONSTANT c_reg_dp_offload_tx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
CONSTANT c_reg_dp_offload_tx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_dat_nof_words);
CONSTANT c_reg_dp_offload_tx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_tx_hdr_dat_adr_w));
CONSTANT c_reg_dp_offload_tx_hdr_ovr_nof_words : NATURAL := g_hdr_field_arr'LENGTH;
CONSTANT c_reg_dp_offload_tx_hdr_ovr_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_ovr_nof_words);
CONSTANT c_reg_dp_offload_tx_hdr_ovr_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_tx_hdr_ovr_adr_w));
CONSTANT c_reg_dp_offload_rx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
CONSTANT c_reg_dp_offload_rx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_hdr_dat_nof_words);
CONSTANT c_reg_dp_offload_rx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_rx_hdr_dat_adr_w));
-- tr_10GbE
CONSTANT c_reg_tr_10GbE_adr_w : NATURAL := 13;
CONSTANT c_reg_tr_10GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_tr_10GbE_adr_w));
-- BSN monitors
CONSTANT c_reg_rsp_bsn_monitor_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_unb2_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
-- Simulation
CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz
CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
--CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
SIGNAL sim_eth_mm_bus_switch : STD_LOGIC;
SIGNAL sim_eth_psc_access : STD_LOGIC;
SIGNAL i_eth1g_reg_mosi : t_mem_mosi;
SIGNAL i_eth1g_reg_miso : t_mem_miso;
SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;
----------------------------------------------------------------------------
-- mm_file component
----------------------------------------------------------------------------
COMPONENT mm_file
GENERIC(
g_file_prefix : STRING;
g_update_on_change : BOOLEAN := FALSE;
g_mm_rd_latency : NATURAL := 1
);
PORT (
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
mm_master_out : OUT t_mem_mosi;
mm_master_in : IN t_mem_miso
);
END COMPONENT;
BEGIN
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
u_mm_file_reg_dp_offload_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_mosi, reg_dp_offload_tx_miso );
u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
u_mm_file_reg_dp_offload_tx_hdr_ovr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_OVR")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_ovr_mosi, reg_dp_offload_tx_hdr_ovr_miso );
u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
u_mm_file_reg_bsn_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
u_mm_file_ram_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
u_mm_file_reg_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
--u_mm_file_reg_tr_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE", c_mm_clk_period, FALSE, 0)
-- PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
----------------------------------------------------------------------------
p_eth_setup : PROCESS
BEGIN
sim_eth_mm_bus_switch <= '1';
eth1g_tse_mosi.wr <= '0';
eth1g_tse_mosi.rd <= '0';
WAIT FOR 400 ns;
WAIT UNTIL rising_edge(mm_clk);
-- proc_tech_tse_setup(c_tech_arria10, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
-- Enable RX
-- proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
sim_eth_mm_bus_switch <= '0';
WAIT;
END PROCESS;
p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
BEGIN
IF sim_eth_mm_bus_switch = '1' THEN
eth1g_reg_mosi <= sim_eth1g_reg_mosi;
ELSE
eth1g_reg_mosi <= i_eth1g_reg_mosi;
END IF;
END PROCESS;
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
END GENERATE;
----------------------------------------------------------------------------
-- QSYS for synthesis
----------------------------------------------------------------------------
gen_qsys : IF g_sim = FALSE GENERATE
u_qsys : qsys_unb2_test
PORT MAP (
clk_clk => mm_clk,
reset_reset_n => mm_rst,
-- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
pio_wdi_external_connection_export => pout_wdi,
avs_eth_0_reset_export => OPEN,
avs_eth_0_clk_export => OPEN,
avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
avs_eth_0_irq_export => eth1g_reg_interrupt,
reg_unb_sens_reset_export => OPEN,
reg_unb_sens_clk_export => OPEN,
reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
pio_system_info_reset_export => OPEN,
pio_system_info_clk_export => OPEN,
pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
pio_system_info_write_export => reg_unb_system_info_mosi.wr,
pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
pio_system_info_read_export => reg_unb_system_info_mosi.rd,
pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
reg_wdi_reset_export => OPEN,
reg_wdi_clk_export => OPEN,
reg_wdi_address_export => reg_wdi_mosi.address(0),
reg_wdi_write_export => reg_wdi_mosi.wr,
reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_wdi_read_export => reg_wdi_mosi.rd,
reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
reg_remu_reset_export => OPEN,
reg_remu_clk_export => OPEN,
reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
reg_remu_write_export => reg_remu_mosi.wr,
reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_remu_read_export => reg_remu_mosi.rd,
reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
reg_epcs_reset_export => OPEN,
reg_epcs_clk_export => OPEN,
reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
reg_epcs_write_export => reg_epcs_mosi.wr,
reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_epcs_read_export => reg_epcs_mosi.rd,
reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
reg_dpmm_ctrl_reset_export => OPEN,
reg_dpmm_ctrl_clk_export => OPEN,
reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0),
reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
reg_mmdp_data_reset_export => OPEN,
reg_mmdp_data_clk_export => OPEN,
reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0),
reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w-1 DOWNTO 0),
reg_dpmm_data_reset_export => OPEN,
reg_dpmm_data_clk_export => OPEN,
reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0),
reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w-1 DOWNTO 0),
reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_mmdp_ctrl_reset_export => OPEN,
reg_mmdp_ctrl_clk_export => OPEN,
reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0),
reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_tr_10gbe_reset_export => OPEN,
reg_tr_10gbe_clk_export => OPEN,
reg_tr_10gbe_address_export => reg_tr_10GbE_mosi.address(c_reg_tr_10GbE_multi_adr_w-1 DOWNTO 0),
reg_tr_10gbe_write_export => reg_tr_10GbE_mosi.wr,
reg_tr_10gbe_writedata_export => reg_tr_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_tr_10gbe_read_export => reg_tr_10GbE_mosi.rd,
reg_tr_10gbe_readdata_export => reg_tr_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
reg_tr_10gbe_waitrequest_export => reg_tr_10GbE_miso.waitrequest,
reg_bsn_monitor_reset_export => OPEN,
reg_bsn_monitor_clk_export => OPEN,
reg_bsn_monitor_address_export => reg_bsn_monitor_mosi.address(c_reg_rsp_bsn_monitor_adr_w-1 DOWNTO 0),
reg_bsn_monitor_write_export => reg_bsn_monitor_mosi.wr,
reg_bsn_monitor_writedata_export => reg_bsn_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_read_export => reg_bsn_monitor_mosi.rd,
reg_bsn_monitor_readdata_export => reg_bsn_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
reg_dp_offload_tx_reset_export => OPEN,
reg_dp_offload_tx_clk_export => OPEN,
reg_dp_offload_tx_address_export => reg_dp_offload_tx_mosi.address(c_reg_dp_offload_tx_multi_adr_w-1 DOWNTO 0),
reg_dp_offload_tx_write_export => reg_dp_offload_tx_mosi.wr,
reg_dp_offload_tx_writedata_export => reg_dp_offload_tx_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_dp_offload_tx_read_export => reg_dp_offload_tx_mosi.rd,
reg_dp_offload_tx_readdata_export => reg_dp_offload_tx_miso.rddata(c_word_w-1 DOWNTO 0),
reg_dp_offload_tx_hdr_dat_reset_export => OPEN,
reg_dp_offload_tx_hdr_dat_clk_export => OPEN,
reg_dp_offload_tx_hdr_dat_address_export => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w-1 DOWNTO 0),
reg_dp_offload_tx_hdr_dat_write_export => reg_dp_offload_tx_hdr_dat_mosi.wr,
reg_dp_offload_tx_hdr_dat_writedata_export => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_dp_offload_tx_hdr_dat_read_export => reg_dp_offload_tx_hdr_dat_mosi.rd,
reg_dp_offload_tx_hdr_dat_readdata_export => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
reg_dp_offload_rx_hdr_dat_reset_export => OPEN,
reg_dp_offload_rx_hdr_dat_clk_export => OPEN,
reg_dp_offload_rx_hdr_dat_address_export => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w-1 DOWNTO 0),
reg_dp_offload_rx_hdr_dat_write_export => reg_dp_offload_rx_hdr_dat_mosi.wr,
reg_dp_offload_rx_hdr_dat_writedata_export => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_dp_offload_rx_hdr_dat_read_export => reg_dp_offload_rx_hdr_dat_mosi.rd,
reg_dp_offload_rx_hdr_dat_readdata_export => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
reg_dp_offload_tx_hdr_ovr_reset_export => OPEN,
reg_dp_offload_tx_hdr_ovr_clk_export => OPEN,
reg_dp_offload_tx_hdr_ovr_address_export => reg_dp_offload_tx_hdr_ovr_mosi.address(c_reg_dp_offload_tx_hdr_ovr_multi_adr_w-1 DOWNTO 0),
reg_dp_offload_tx_hdr_ovr_write_export => reg_dp_offload_tx_hdr_ovr_mosi.wr,
reg_dp_offload_tx_hdr_ovr_writedata_export => reg_dp_offload_tx_hdr_ovr_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_dp_offload_tx_hdr_ovr_read_export => reg_dp_offload_tx_hdr_ovr_mosi.rd,
reg_dp_offload_tx_hdr_ovr_readdata_export => reg_dp_offload_tx_hdr_ovr_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diag_data_buffer_reset_export => OPEN,
reg_diag_data_buffer_clk_export => OPEN,
reg_diag_data_buffer_address_export => reg_diag_data_buf_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
reg_diag_data_buffer_write_export => reg_diag_data_buf_mosi.wr,
reg_diag_data_buffer_writedata_export => reg_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_data_buffer_read_export => reg_diag_data_buf_mosi.rd,
reg_diag_data_buffer_readdata_export => reg_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
ram_diag_data_buffer_clk_export => OPEN,
ram_diag_data_buffer_reset_export => OPEN,
ram_diag_data_buffer_address_export => ram_diag_data_buf_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
ram_diag_data_buffer_write_export => ram_diag_data_buf_mosi.wr,
ram_diag_data_buffer_writedata_export => ram_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buffer_read_export => ram_diag_data_buf_mosi.rd,
ram_diag_data_buffer_readdata_export => ram_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diag_bg_reset_export => OPEN,
reg_diag_bg_clk_export => OPEN,
reg_diag_bg_address_export => reg_diag_bg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
reg_diag_bg_write_export => reg_diag_bg_mosi.wr,
reg_diag_bg_writedata_export => reg_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_bg_read_export => reg_diag_bg_mosi.rd,
reg_diag_bg_readdata_export => reg_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
ram_diag_bg_reset_export => OPEN,
ram_diag_bg_clk_export => OPEN,
ram_diag_bg_address_export => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w-1 DOWNTO 0),
ram_diag_bg_write_export => ram_diag_bg_mosi.wr,
ram_diag_bg_writedata_export => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_bg_read_export => ram_diag_bg_mosi.rd,
ram_diag_bg_readdata_export => ram_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
END str;
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE qsys_unb2_test_pkg IS
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v14 QSYS builder
-----------------------------------------------------------------------------
COMPONENT qsys_unb2_test is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
pio_wdi_external_connection_export : out std_logic; -- export
avs_eth_0_reset_export : out std_logic; -- export
avs_eth_0_clk_export : out std_logic; -- export
avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
avs_eth_0_tse_write_export : out std_logic; -- export
avs_eth_0_tse_read_export : out std_logic; -- export
avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
avs_eth_0_reg_write_export : out std_logic; -- export
avs_eth_0_reg_read_export : out std_logic; -- export
avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
avs_eth_0_ram_write_export : out std_logic; -- export
avs_eth_0_ram_read_export : out std_logic; -- export
avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
avs_eth_0_irq_export : in std_logic := 'X'; -- export
reg_unb_sens_reset_export : out std_logic; -- export
reg_unb_sens_clk_export : out std_logic; -- export
reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
reg_unb_sens_write_export : out std_logic; -- export
reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_unb_sens_read_export : out std_logic; -- export
reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
rom_system_info_reset_export : out std_logic; -- export
rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
rom_system_info_clk_export : out std_logic; -- export
rom_system_info_write_export : out std_logic; -- export
rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
rom_system_info_read_export : out std_logic; -- export
rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
pio_system_info_reset_export : out std_logic; -- export
pio_system_info_clk_export : out std_logic; -- export
pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
pio_system_info_write_export : out std_logic; -- export
pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
pio_system_info_read_export : out std_logic; -- export
pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
pio_pps_reset_export : out std_logic; -- export
pio_pps_clk_export : out std_logic; -- export
pio_pps_address_export : out std_logic;--_vector(0 downto 0); -- export
pio_pps_write_export : out std_logic; -- export
pio_pps_read_export : out std_logic; -- export
pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_wdi_reset_export : out std_logic; -- export
reg_wdi_clk_export : out std_logic; -- export
reg_wdi_address_export : out std_logic;--_vector(0 downto 0); -- export
reg_wdi_write_export : out std_logic; -- export
reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_wdi_read_export : out std_logic; -- export
reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_remu_reset_export : out std_logic; -- export
reg_remu_clk_export : out std_logic; -- export
reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
reg_remu_write_export : out std_logic; -- export
reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_remu_read_export : out std_logic; -- export
reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_epcs_reset_export : out std_logic; -- export
reg_epcs_clk_export : out std_logic; -- export
reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
reg_epcs_write_export : out std_logic; -- export
reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_epcs_read_export : out std_logic; -- export
reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_dpmm_ctrl_reset_export : out std_logic; -- export
reg_dpmm_ctrl_clk_export : out std_logic; -- export
reg_dpmm_ctrl_address_export : out std_logic;--_vector(0 downto 0); -- export
reg_dpmm_ctrl_write_export : out std_logic; -- export
reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dpmm_ctrl_read_export : out std_logic; -- export
reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_mmdp_data_reset_export : out std_logic; -- export
reg_mmdp_data_clk_export : out std_logic; -- export
reg_mmdp_data_address_export : out std_logic;--_vector(0 downto 0); -- export
reg_mmdp_data_write_export : out std_logic; -- export
reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_mmdp_data_read_export : out std_logic; -- export
reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_mmdp_ctrl_read_export : out std_logic; -- export
reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_mmdp_ctrl_write_export : out std_logic; -- export
reg_mmdp_ctrl_address_export : out std_logic;--_vector(0 downto 0); -- export
reg_mmdp_ctrl_clk_export : out std_logic; -- export
reg_mmdp_ctrl_reset_export : out std_logic; -- export
reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_dpmm_data_read_export : out std_logic; -- export
reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dpmm_data_write_export : out std_logic; -- export
reg_dpmm_data_address_export : out std_logic;--_vector(0 downto 0); -- export
reg_dpmm_data_clk_export : out std_logic; -- export
reg_dpmm_data_reset_export : out std_logic; -- export
reg_tr_10gbe_reset_export : out std_logic; -- export
reg_tr_10gbe_clk_export : out std_logic; -- export
reg_tr_10gbe_address_export : out std_logic_vector(14 downto 0); -- export
reg_tr_10gbe_write_export : out std_logic; -- export
reg_tr_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_tr_10gbe_read_export : out std_logic; -- export
reg_tr_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_tr_10gbe_waitrequest_export : in std_logic := 'X'; -- export
reg_bsn_monitor_reset_export : out std_logic; -- export
reg_bsn_monitor_clk_export : out std_logic; -- export
reg_bsn_monitor_address_export : out std_logic_vector(5 downto 0); -- export
reg_bsn_monitor_write_export : out std_logic; -- export
reg_bsn_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_bsn_monitor_read_export : out std_logic; -- export
reg_bsn_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_dp_offload_tx_reset_export : out std_logic; -- export
reg_dp_offload_tx_clk_export : out std_logic; -- export
reg_dp_offload_tx_address_export : out std_logic_vector(2 downto 0); -- export
reg_dp_offload_tx_write_export : out std_logic; -- export
reg_dp_offload_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_tx_read_export : out std_logic; -- export
reg_dp_offload_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_dp_offload_tx_hdr_dat_reset_export : out std_logic; -- export
reg_dp_offload_tx_hdr_dat_clk_export : out std_logic; -- export
reg_dp_offload_tx_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
reg_dp_offload_tx_hdr_dat_write_export : out std_logic; -- export
reg_dp_offload_tx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_tx_hdr_dat_read_export : out std_logic; -- export
reg_dp_offload_tx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_dp_offload_rx_hdr_dat_reset_export : out std_logic; -- export
reg_dp_offload_rx_hdr_dat_clk_export : out std_logic; -- export
reg_dp_offload_rx_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
reg_dp_offload_rx_hdr_dat_write_export : out std_logic; -- export
reg_dp_offload_rx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_rx_hdr_dat_read_export : out std_logic; -- export
reg_dp_offload_rx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_dp_offload_tx_hdr_ovr_reset_export : out std_logic; -- export
reg_dp_offload_tx_hdr_ovr_clk_export : out std_logic; -- export
reg_dp_offload_tx_hdr_ovr_address_export : out std_logic_vector(6 downto 0); -- export
reg_dp_offload_tx_hdr_ovr_write_export : out std_logic; -- export
reg_dp_offload_tx_hdr_ovr_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_tx_hdr_ovr_read_export : out std_logic; -- export
reg_dp_offload_tx_hdr_ovr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_data_buffer_reset_export : out std_logic; -- export
reg_diag_data_buffer_clk_export : out std_logic; -- export
reg_diag_data_buffer_address_export : out std_logic_vector(4 downto 0); -- export
reg_diag_data_buffer_write_export : out std_logic; -- export
reg_diag_data_buffer_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_data_buffer_read_export : out std_logic; -- export
reg_diag_data_buffer_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_diag_data_buffer_clk_export : out std_logic; -- export
ram_diag_data_buffer_reset_export : out std_logic; -- export
ram_diag_data_buffer_address_export : out std_logic_vector(13 downto 0); -- export
ram_diag_data_buffer_write_export : out std_logic; -- export
ram_diag_data_buffer_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_data_buffer_read_export : out std_logic; -- export
ram_diag_data_buffer_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_bg_reset_export : out std_logic; -- export
reg_diag_bg_clk_export : out std_logic; -- export
reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
reg_diag_bg_write_export : out std_logic; -- export
reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_bg_read_export : out std_logic; -- export
reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_diag_bg_reset_export : out std_logic; -- export
ram_diag_bg_clk_export : out std_logic; -- export
ram_diag_bg_address_export : out std_logic_vector(11 downto 0); -- export
ram_diag_bg_write_export : out std_logic; -- export
ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_bg_read_export : out std_logic; -- export
ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
);
END COMPONENT qsys_unb2_test;
END qsys_unb2_test_pkg;
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2_board_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_interface_layers_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE unb2_board_lib.unb2_board_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE eth_lib.eth_pkg.ALL;
ENTITY unb2_test IS
GENERIC (
g_design_name : STRING := "unb2_test";
g_design_note : STRING := "UNUSED";
g_technology : NATURAL := c_tech_arria10;
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
);
PORT (
-- GENERAL
--CLK : IN STD_LOGIC; -- System Clock - not used as PLL generates dp_clk.
PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
SENS_SC : INOUT STD_LOGIC;
SENS_SD : INOUT STD_LOGIC;
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
-- Transceiver clocks
SA_CLK : IN STD_LOGIC; -- SerDes Clock 10GbE front and ring
SB_CLK : IN STD_LOGIC; -- SerDes Clock 10GbE back
BCK_REF_CLK : IN STD_LOGIC; --
-- back transceivers
-- BCK_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0);
-- BCK_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0);
-- BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
-- BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
-- BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
-- ring transceivers
-- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : INOUT STD_LOGIC;
PMBUS_SD : INOUT STD_LOGIC;
PMBUS_ALERT : IN STD_LOGIC;
-- front transceivers
QSFP_0_RX : IN STD_LOGIC_VECTOR(0 downto 0); --c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_0_TX : OUT STD_LOGIC_VECTOR(0 downto 0); --c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
QSFP_RST : INOUT STD_LOGIC;
QSFP_LED : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
);
END unb2_test;
ARCHITECTURE str OF unb2_test IS
-- Firmware version x.y
CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 1);
CONSTANT c_lpbk_data_w : NATURAL := 32; -- 128 c_eth_data_w, c_xgmii_data_w
-- Revision controlled constants
CONSTANT c_use_lpbk : BOOLEAN := FALSE; --g_design_name = "unb2_test_lpbk";
CONSTANT c_use_1GbE : BOOLEAN := FALSE; --g_design_name = "unb2_test_1GbE";
CONSTANT c_use_10GbE : BOOLEAN := TRUE; --g_design_name = "unb2_test_10GbE";
CONSTANT c_nof_streams : NATURAL := 1; --c_unb2_board_tr_qsfp_hw_nof_lines; --FIXME
CONSTANT c_data_w : NATURAL := sel_a_b(c_use_lpbk, c_lpbk_data_w, -- Select correct c_data_w when one interface is used
sel_a_b(c_use_1GbE, c_eth_data_w,
sel_a_b(c_use_10GbE, c_xgmii_data_w, 0)));
-- Block generator
CONSTANT c_bg_block_size : NATURAL := 900;
CONSTANT c_bg_gapsize : NATURAL := 100;
CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
'0', -- enable_sync
TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
TO_UVEC( 0, c_diag_bg_bsn_init_w));
-- dp_offload_tx
CONSTANT c_nof_hdr_fields : NATURAL := 4+12+4+9; -- Total header bits = 512
CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111011111100"&"0001"&"101111111";
CONSTANT c_use_jumbo_frames : BOOLEAN := TRUE;
CONSTANT c_def_1GbE_block_size : NATURAL := 0; -- 0 first so we have time to set RX demux reg in dest. node
CONSTANT c_def_10GbE_block_size : NATURAL := 700; -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
CONSTANT c_max_frame_len : NATURAL := sel_a_b(c_use_jumbo_frames, 9018, 1518);
CONSTANT c_max_frame_nof_words : NATURAL := (c_max_frame_len * c_byte_w ) / c_data_w;
CONSTANT c_nof_header_words : NATURAL := field_slv_len(c_hdr_field_arr) / c_data_w;
CONSTANT c_nof_header_bytes : NATURAL := field_slv_len(c_hdr_field_arr) / c_byte_w;
CONSTANT c_nof_crc_words : NATURAL := 1;
CONSTANT c_max_udp_payload_len : NATURAL := c_max_frame_len-c_nof_header_bytes-c_network_eth_crc_len;
CONSTANT c_max_udp_payload_nof_words : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w;
CONSTANT c_max_nof_words_per_block : NATURAL := c_bg_block_size;
CONSTANT c_min_nof_words_per_block : NATURAL := 1;
CONSTANT c_def_nof_words_per_block : NATURAL := sel_a_b(c_use_1GbE, c_def_1GbE_block_size,
sel_a_b(c_use_10GbE, c_def_10GbE_block_size,
c_bg_block_size));
CONSTANT c_max_nof_blocks_per_packet : NATURAL := c_max_udp_payload_nof_words/c_min_nof_words_per_block;
CONSTANT c_def_nof_blocks_per_packet : NATURAL := 1;
SIGNAL hdr_fields_in_arr : t_slv_1024_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL hdr_fields_out_arr : t_slv_1024_arr(c_nof_streams-1 DOWNTO 0);
-- System
SIGNAL cs_sim : STD_LOGIC;
SIGNAL xo_ethclk : STD_LOGIC;
SIGNAL xo_rst : STD_LOGIC;
SIGNAL xo_rst_n : STD_LOGIC;
SIGNAL mm_clk : STD_LOGIC;
SIGNAL mm_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC;
SIGNAL dp_rst : STD_LOGIC;
-- PIOs
SIGNAL pout_wdi : STD_LOGIC;
-- WDI override
SIGNAL reg_wdi_mosi : t_mem_mosi;
SIGNAL reg_wdi_miso : t_mem_miso;
-- PPSH
SIGNAL reg_ppsh_mosi : t_mem_mosi;
SIGNAL reg_ppsh_miso : t_mem_miso;
-- UniBoard system info
SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
SIGNAL reg_unb_system_info_miso : t_mem_miso;
SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
SIGNAL rom_unb_system_info_miso : t_mem_miso;
-- UniBoard I2C sens
SIGNAL reg_unb_sens_mosi : t_mem_mosi;
SIGNAL reg_unb_sens_miso : t_mem_miso;
-- eth1g
SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
SIGNAL eth1g_tse_miso : t_mem_miso;
SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
SIGNAL eth1g_reg_miso : t_mem_miso;
SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
SIGNAL eth1g_ram_miso : t_mem_miso;
-- EPCS read
SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
SIGNAL reg_dpmm_data_miso : t_mem_miso;
SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi;
SIGNAL reg_dpmm_ctrl_miso : t_mem_miso;
-- EPCS write
SIGNAL reg_mmdp_data_mosi : t_mem_mosi;
SIGNAL reg_mmdp_data_miso : t_mem_miso;
SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi;
SIGNAL reg_mmdp_ctrl_miso : t_mem_miso;
-- EPCS status/control
SIGNAL reg_epcs_mosi : t_mem_mosi;
SIGNAL reg_epcs_miso : t_mem_miso;
-- Remote Update
SIGNAL reg_remu_mosi : t_mem_mosi;
SIGNAL reg_remu_miso : t_mem_miso;
-- 10GbE
SIGNAL serial_10G_tx_arr : STD_LOGIC_VECTOR(c_nof_streams-1 downto 0);
SIGNAL serial_10G_rx_arr : STD_LOGIC_VECTOR(c_nof_streams-1 downto 0);
SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
SIGNAL reg_tr_10GbE_miso : t_mem_miso;
SIGNAL reg_dp_ram_from_mm_mosi : t_mem_mosi;
SIGNAL reg_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL ram_dp_ram_from_mm_mosi : t_mem_mosi;
SIGNAL ram_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL ram_dp_ram_to_mm_mosi : t_mem_mosi;
SIGNAL ram_dp_ram_to_mm_miso : t_mem_miso;
SIGNAL reg_diag_bg_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_miso : t_mem_miso;
SIGNAL ram_diag_bg_mosi : t_mem_mosi;
SIGNAL ram_diag_bg_miso : t_mem_miso;
SIGNAL reg_dp_offload_tx_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_tx_miso : t_mem_miso;
SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
SIGNAL reg_dp_offload_tx_hdr_ovr_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_tx_hdr_ovr_miso : t_mem_miso;
SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
SIGNAL reg_bsn_monitor_mosi : t_mem_mosi;
SIGNAL reg_bsn_monitor_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_miso : t_mem_miso;
SIGNAL block_gen_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL block_gen_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL diag_data_buf_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
-- Interface: 1GbE UDP streaming ports
SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
BEGIN
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : ENTITY unb2_board_lib.ctrl_unb2_board
GENERIC MAP (
g_sim => g_sim,
g_design_name => g_design_name,
g_design_note => g_design_note,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn,
g_fw_version => c_fw_version,
g_mm_clk_freq => c_unb2_board_mm_clk_freq_125M,
g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
g_aux => c_unb2_board_aux,
g_udp_offload => c_use_1GbE,
g_udp_offload_nof_streams => c_nof_streams,
g_dp_clk_use_pll => FALSE
)
PORT MAP (
-- Clock an reset signals
cs_sim => cs_sim,
xo_ethclk => xo_ethclk,
xo_rst => xo_rst,
xo_rst_n => xo_rst_n,
mm_clk => mm_clk,
mm_rst => mm_rst,
dp_rst => dp_rst,
dp_clk => OPEN,
dp_pps => OPEN,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
-- Toggle WDI
pout_wdi => pout_wdi,
-- MM buses
-- REMU
reg_remu_mosi => reg_remu_mosi,
reg_remu_miso => reg_remu_miso,
-- EPCS read
reg_dpmm_data_mosi => reg_dpmm_data_mosi,
reg_dpmm_data_miso => reg_dpmm_data_miso,
reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-- EPCS write
reg_mmdp_data_mosi => reg_mmdp_data_mosi,
reg_mmdp_data_miso => reg_mmdp_data_miso,
reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-- EPCS status/control
reg_epcs_mosi => reg_epcs_mosi,
reg_epcs_miso => reg_epcs_miso,
-- . Manual WDI override
reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso,
-- . System_info
reg_unb_system_info_mosi => reg_unb_system_info_mosi,
reg_unb_system_info_miso => reg_unb_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi,
rom_unb_system_info_miso => rom_unb_system_info_miso,
-- . UniBoard I2C sensors
reg_unb_sens_mosi => reg_unb_sens_mosi,
reg_unb_sens_miso => reg_unb_sens_miso,
-- . PPSH
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
eth1g_reg_mosi => eth1g_reg_mosi,
eth1g_reg_miso => eth1g_reg_miso,
eth1g_reg_interrupt => eth1g_reg_interrupt,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
-- eth1g UDP streaming ports
udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
-- FPGA pins
-- . General
CLK => '0', -- PLL generated 200MHz dp_clk is used.
PPS => PPS,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- . Others
VERSION => VERSION,
ID => ID,
TESTIO => TESTIO,
-- . I2C Interface to Sensors
SENS_SC => SENS_SC,
SENS_SD => SENS_SD,
-- . 1GbE Control Interface
ETH_CLK => ETH_CLK,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT
);
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : ENTITY work.mmm_unb2_test
GENERIC MAP (
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_nof_streams => 3, --c_nof_streams, --FIXME
g_bg_block_size => c_bg_block_size,
g_hdr_field_arr => c_hdr_field_arr
)
PORT MAP(
mm_rst => mm_rst,
mm_clk => mm_clk,
-- PIOs
pout_wdi => pout_wdi,
-- Manual WDI override
reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso,
-- system_info
reg_unb_system_info_mosi => reg_unb_system_info_mosi,
reg_unb_system_info_miso => reg_unb_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi,
rom_unb_system_info_miso => rom_unb_system_info_miso,
-- UniBoard I2C sensors
reg_unb_sens_mosi => reg_unb_sens_mosi,
reg_unb_sens_miso => reg_unb_sens_miso,
-- PPSH
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
eth1g_reg_mosi => eth1g_reg_mosi,
eth1g_reg_miso => eth1g_reg_miso,
eth1g_reg_interrupt => eth1g_reg_interrupt,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
-- EPCS read
reg_dpmm_data_mosi => reg_dpmm_data_mosi,
reg_dpmm_data_miso => reg_dpmm_data_miso,
reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-- EPCS write
reg_mmdp_data_mosi => reg_mmdp_data_mosi,
reg_mmdp_data_miso => reg_mmdp_data_miso,
reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-- EPCS status/control
reg_epcs_mosi => reg_epcs_mosi,
reg_epcs_miso => reg_epcs_miso,
-- Remote Update
reg_remu_mosi => reg_remu_mosi,
reg_remu_miso => reg_remu_miso,
-- bg
ram_diag_bg_mosi => ram_diag_bg_mosi,
ram_diag_bg_miso => ram_diag_bg_miso,
reg_diag_bg_mosi => reg_diag_bg_mosi,
reg_diag_bg_miso => reg_diag_bg_miso,
-- dp_offload
reg_dp_offload_tx_mosi => reg_dp_offload_tx_mosi,
reg_dp_offload_tx_miso => reg_dp_offload_tx_miso,
reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
reg_dp_offload_tx_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
reg_dp_offload_tx_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso,
reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-- bsn_monitor
reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-- db
ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
ram_diag_data_buf_miso => ram_diag_data_buf_miso,
reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-- 10GbE
reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
reg_tr_10GbE_miso => reg_tr_10GbE_miso
);
-----------------------------------------------------------------------------
-- TX: Block generator
-----------------------------------------------------------------------------
u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
GENERIC MAP (
g_nof_output_streams => c_nof_streams,
g_buf_dat_w => c_data_w,
g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
g_file_name_prefix => "../../counter_data_" & NATURAL'IMAGE(c_data_w),
g_diag_block_gen_rst => c_bg_ctrl
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
out_sosi_arr => block_gen_src_out_arr,
out_siso_arr => block_gen_src_in_arr,
reg_bg_ctrl_mosi => reg_diag_bg_mosi,
reg_bg_ctrl_miso => reg_diag_bg_miso,
ram_bg_data_mosi => ram_diag_bg_mosi,
ram_bg_data_miso => ram_diag_bg_miso
);
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : ENTITY dp_lib.dp_offload_tx_dev
GENERIC MAP (
g_nof_streams => c_nof_streams,
g_data_w => c_data_w,
g_use_complex => FALSE,
g_max_nof_words_per_block => c_max_nof_words_per_block,
g_def_nof_words_per_block => c_def_nof_words_per_block,
g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet,
g_def_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
g_output_fifo_depth => c_max_frame_nof_words,
g_hdr_field_arr => c_hdr_field_arr,
g_hdr_field_ovr_init => c_hdr_field_ovr_init
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
reg_mosi => reg_dp_offload_tx_mosi,
reg_miso => reg_dp_offload_tx_miso,
reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
reg_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
reg_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso,
snk_in_arr => block_gen_src_out_arr,
snk_out_arr => block_gen_src_in_arr,
src_out_arr => dp_offload_tx_src_out_arr,
src_in_arr => dp_offload_tx_src_in_arr,
hdr_fields_in_arr => hdr_fields_in_arr
);
gen_hdr_in_fields : FOR i IN 0 TO c_nof_streams-1 GENERATE
-- dst = src
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_dst_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_dst_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr")) <= x"0A63" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_dst_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_dst_addr")) <= x"0A63" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
-- dst port goes through 4000,4001,4002
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_src_port") DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= TO_UVEC(4000+i, 16);
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_dst_port") DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= TO_UVEC(4000+i, 16);
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_sync" ) DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )) <= slv(block_gen_src_out_arr(i).sync);
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )) <= block_gen_src_out_arr(i).bsn(59 DOWNTO 0);
END GENERATE;
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx_dev
GENERIC MAP (
g_nof_streams => c_nof_streams,
g_data_w => c_data_w,
g_hdr_field_arr => c_hdr_field_arr,
g_remove_crc => NOT(c_use_lpbk),
g_crc_nof_words => c_nof_crc_words
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
snk_in_arr => dp_offload_rx_snk_in_arr,
snk_out_arr => dp_offload_rx_snk_out_arr,
src_out_arr => dp_offload_rx_src_out_arr,
src_in_arr => dp_offload_rx_src_in_arr,
hdr_fields_out_arr => hdr_fields_out_arr
);
gen_hdr_out_fields : FOR i IN 0 TO c_nof_streams-1 GENERATE
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )));
diag_data_buf_snk_in_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )), c_dp_stream_bsn_w);
END GENERATE;
-----------------------------------------------------------------------------
-- RX: Data buffers and BSN monitors
-----------------------------------------------------------------------------
dp_offload_rx_src_in_arr <= diag_data_buf_snk_out_arr;
gen_bsn_mon_in : FOR i IN 0 TO c_nof_streams-1 GENERATE
diag_data_buf_snk_in_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
diag_data_buf_snk_in_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
diag_data_buf_snk_in_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
diag_data_buf_snk_in_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
diag_data_buf_snk_in_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
END GENERATE;
u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
GENERIC MAP (
g_nof_streams => c_nof_streams,
g_cross_clock_domain => TRUE,
g_sync_timeout => c_bg_blocks_per_sync*(c_bg_block_size+c_bg_gapsize),
g_cnt_sop_w => ceil_log2(c_bg_blocks_per_sync+1),
g_cnt_valid_w => ceil_log2(c_bg_blocks_per_sync*c_bg_block_size+1),
g_log_first_bsn => TRUE
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
reg_mosi => reg_bsn_monitor_mosi,
reg_miso => reg_bsn_monitor_miso,
dp_rst => dp_rst,
dp_clk => dp_clk,
in_siso_arr => diag_data_buf_snk_out_arr,
in_sosi_arr => diag_data_buf_snk_in_arr
);
diag_data_buf_snk_out_arr <= (OTHERS=>c_dp_siso_rdy);
u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_nof_streams => c_nof_streams,
g_data_w => 32, --c_data_w,
g_buf_nof_data => 1024,
g_buf_use_sync => FALSE -- sync by reading last address of data buffer
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
ram_data_buf_mosi => ram_diag_data_buf_mosi,
ram_data_buf_miso => ram_diag_data_buf_miso,
reg_data_buf_mosi => reg_diag_data_buf_mosi,
reg_data_buf_miso => reg_diag_data_buf_miso,
--in_sync => diag_data_buf_snk_in_arr(0).sop,
in_sync => diag_data_buf_snk_in_arr(0).sync,
in_sosi_arr => diag_data_buf_snk_in_arr
);
-----------------------------------------------------------------------------
-- Interface : Loopback
-----------------------------------------------------------------------------
gen_loopback : IF c_use_lpbk=TRUE GENERATE
dp_offload_rx_snk_in_arr <= dp_offload_tx_src_out_arr;
dp_offload_tx_src_in_arr <= (OTHERS=>c_dp_siso_rdy);
END GENERATE;
-----------------------------------------------------------------------------
-- Interface : 1GbE
-----------------------------------------------------------------------------
gen_wires_1GbE : IF c_use_1GbE=TRUE GENERATE
eth1g_udp_tx_sosi_arr <= dp_offload_tx_src_out_arr;
dp_offload_tx_src_in_arr <= eth1g_udp_tx_siso_arr;
dp_offload_rx_snk_in_arr <= eth1g_udp_rx_sosi_arr;
eth1g_udp_rx_siso_arr <= dp_offload_rx_snk_out_arr;
END GENERATE;
-----------------------------------------------------------------------------
-- tr_10GbE
-----------------------------------------------------------------------------
gen_tr_10GbE : IF c_use_10GbE=TRUE GENERATE
u_tr_10GbE_front_and_ring: ENTITY unb2_board_lib.unb2_board_10gbe_front_and_ring
GENERIC MAP (
g_technology => g_technology,
g_sim => g_sim,
g_sim_level => 1,
g_nof_macs => c_nof_streams,
g_tx_fifo_fill => c_def_10GbE_block_size,
g_tx_fifo_size => c_def_10GbE_block_size*2
)
PORT MAP (
tr_ref_clk => SA_CLK,
-- MM interface
mm_rst => mm_rst,
mm_clk => mm_clk,
reg_mac_mosi => reg_tr_10GbE_mosi,
reg_mac_miso => reg_tr_10GbE_miso,
-- DP interface
dp_rst => dp_rst,
dp_clk => dp_clk,
src_out_arr => dp_offload_rx_snk_in_arr,
src_in_arr => dp_offload_rx_snk_out_arr,
snk_out_arr => dp_offload_tx_src_in_arr,
snk_in_arr => dp_offload_tx_src_out_arr,
-- Serial IO
serial_tx_arr => serial_10G_tx_arr,
serial_rx_arr => serial_10G_rx_arr
);
u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
PORT MAP (
serial_tx_arr(0 DOWNTO 0) => serial_10G_tx_arr,
serial_rx_arr(0 DOWNTO 0) => serial_10G_rx_arr,
serial_tx_arr(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 1) => (OTHERS=>'0'),
serial_rx_arr(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 1) => OPEN,
-- Serial I/O
-- front transceivers
QSFP_0_RX => QSFP_0_RX,
QSFP_0_TX => QSFP_0_TX,
-- QSFP_1_RX => QSFP_1_RX,
-- QSFP_1_TX => QSFP_1_TX,
-- QSFP_2_RX => QSFP_2_RX,
-- QSFP_2_TX => QSFP_2_TX,
-- QSFP_3_RX => QSFP_3_RX,
-- QSFP_3_TX => QSFP_3_TX,
-- QSFP_4_RX => QSFP_4_RX,
-- QSFP_4_TX => QSFP_4_TX,
-- QSFP_5_RX => QSFP_5_RX,
-- QSFP_5_TX => QSFP_5_TX,
QSFP_SDA => QSFP_SDA,
QSFP_SCL => QSFP_SCL,
QSFP_RST => QSFP_RST,
QSFP_LED => QSFP_LED
);
--u_back_io : ENTITY unb2_board_lib.unb2_board_back_io
--PORT MAP (
-- serial_tx_arr => (OTHERS=>'0'),
-- --serial_rx_arr => ,
-- -- Serial I/O
-- -- back transceivers
-- BCK_RX => BCK_RX,
-- BCK_TX => BCK_TX,
-- BCK_SDA => BCK_SDA,
-- BCK_SCL => BCK_SCL,
-- BCK_ERR => BCK_ERR
--);
--u_ring_io : ENTITY unb2_board_lib.unb2_board_ring_io
--PORT MAP (
-- serial_tx_arr => (OTHERS=>'0'),
-- --serial_rx_arr => ,
-- -- Serial I/O
-- -- ring transceivers
-- RING_0_RX => RING_0_RX,
-- RING_0_TX => RING_0_TX,
-- RING_1_RX => RING_1_RX,
-- RING_1_TX => RING_1_TX
--);
END GENERATE;
-----------------------------------------------------------------------------
-- Node function
-----------------------------------------------------------------------------
-- Insert node_[design_name] here
END str;
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment