Register ref_sync to ease timing closure for ref_sync fanout to (many) dp_bsn_monitor_v2 instances.

libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd

@@ -116,6 +116,7 @@ ARCHITECTURE rtl OF dp_bsn_monitor_v2 IS
   SIGNAL nof_valid                   : STD_LOGIC_VECTOR(c_cnt_valid_w-1 DOWNTO 0);
   SIGNAL cnt_latency                 : STD_LOGIC_VECTOR(c_cnt_latency_w-1 DOWNTO 0);
   SIGNAL latency                     : STD_LOGIC_VECTOR(c_cnt_latency_w-1 DOWNTO 0);
+  SIGNAL ref_sync_reg                : STD_LOGIC := '0';
 
   SIGNAL i_mon_ready_stable          : STD_LOGIC;
   SIGNAL i_mon_xon_stable            : STD_LOGIC;
@@ -167,7 +168,10 @@ BEGIN
   nof_err   <= cnt_err;
   nof_valid <= cnt_valid; 
   latency   <= cnt_latency;
-  
+
+  -- Register ref_sync to ease timing closure for ref_sync fanout to (many) dp_bsn_monitor_v2 instances
+  ref_sync_reg <= ref_sync WHEN rising_edge(clk);
+
   u_sync_timeout_cnt : ENTITY common_lib.common_counter
   GENERIC MAP (
     g_width => c_sync_timeout_w
@@ -315,7 +319,7 @@ BEGIN
     load    => TO_SVEC(1, c_cnt_valid_w),
     count   => cnt_valid
   );
-  
+
   u_cnt_latency : ENTITY common_lib.common_counter
   GENERIC MAP (
     g_width => c_cnt_latency_w
@@ -323,7 +327,7 @@ BEGIN
   PORT MAP (
     rst     => rst,
     clk     => clk,
-    cnt_clr => ref_sync,
+    cnt_clr => ref_sync_reg,
     cnt_en  => '1',
     count   => cnt_latency
   );